1/* 2 * Copyright (C) 1995 Linus Torvalds 3 * Copyright 2010 Tilera Corporation. All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation, version 2. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 12 * NON INFRINGEMENT. See the GNU General Public License for 13 * more details. 14 */ 15 16#include <linux/module.h> 17#include <linux/signal.h> 18#include <linux/sched.h> 19#include <linux/kernel.h> 20#include <linux/errno.h> 21#include <linux/string.h> 22#include <linux/types.h> 23#include <linux/ptrace.h> 24#include <linux/mman.h> 25#include <linux/mm.h> 26#include <linux/hugetlb.h> 27#include <linux/swap.h> 28#include <linux/smp.h> 29#include <linux/init.h> 30#include <linux/highmem.h> 31#include <linux/pagemap.h> 32#include <linux/poison.h> 33#include <linux/bootmem.h> 34#include <linux/slab.h> 35#include <linux/proc_fs.h> 36#include <linux/efi.h> 37#include <linux/memory_hotplug.h> 38#include <linux/uaccess.h> 39#include <asm/mmu_context.h> 40#include <asm/processor.h> 41#include <asm/pgtable.h> 42#include <asm/pgalloc.h> 43#include <asm/dma.h> 44#include <asm/fixmap.h> 45#include <asm/tlb.h> 46#include <asm/tlbflush.h> 47#include <asm/sections.h> 48#include <asm/setup.h> 49#include <asm/homecache.h> 50#include <hv/hypervisor.h> 51#include <arch/chip.h> 52 53#include "migrate.h" 54 55#define clear_pgd(pmdptr) (*(pmdptr) = hv_pte(0)) 56 57#ifndef __tilegx__ 58unsigned long VMALLOC_RESERVE = CONFIG_VMALLOC_RESERVE; 59EXPORT_SYMBOL(VMALLOC_RESERVE); 60#endif 61 62/* Create an L2 page table */ 63static pte_t * __init alloc_pte(void) 64{ 65 return __alloc_bootmem(L2_KERNEL_PGTABLE_SIZE, HV_PAGE_TABLE_ALIGN, 0); 66} 67 68/* 69 * L2 page tables per controller. We allocate these all at once from 70 * the bootmem allocator and store them here. This saves on kernel L2 71 * page table memory, compared to allocating a full 64K page per L2 72 * page table, and also means that in cases where we use huge pages, 73 * we are guaranteed to later be able to shatter those huge pages and 74 * switch to using these page tables instead, without requiring 75 * further allocation. Each l2_ptes[] entry points to the first page 76 * table for the first hugepage-size piece of memory on the 77 * controller; other page tables are just indexed directly, i.e. the 78 * L2 page tables are contiguous in memory for each controller. 79 */ 80static pte_t *l2_ptes[MAX_NUMNODES]; 81static int num_l2_ptes[MAX_NUMNODES]; 82 83static void init_prealloc_ptes(int node, int pages) 84{ 85 BUG_ON(pages & (PTRS_PER_PTE - 1)); 86 if (pages) { 87 num_l2_ptes[node] = pages; 88 l2_ptes[node] = __alloc_bootmem(pages * sizeof(pte_t), 89 HV_PAGE_TABLE_ALIGN, 0); 90 } 91} 92 93pte_t *get_prealloc_pte(unsigned long pfn) 94{ 95 int node = pfn_to_nid(pfn); 96 pfn &= ~(-1UL << (NR_PA_HIGHBIT_SHIFT - PAGE_SHIFT)); 97 BUG_ON(node >= MAX_NUMNODES); 98 BUG_ON(pfn >= num_l2_ptes[node]); 99 return &l2_ptes[node][pfn]; 100} 101 102/* 103 * What caching do we expect pages from the heap to have when 104 * they are allocated during bootup? (Once we've installed the 105 * "real" swapper_pg_dir.) 106 */ 107static int initial_heap_home(void) 108{ 109 if (hash_default) 110 return PAGE_HOME_HASH; 111 return smp_processor_id(); 112} 113 114/* 115 * Place a pointer to an L2 page table in a middle page 116 * directory entry. 117 */ 118static void __init assign_pte(pmd_t *pmd, pte_t *page_table) 119{ 120 phys_addr_t pa = __pa(page_table); 121 unsigned long l2_ptfn = pa >> HV_LOG2_PAGE_TABLE_ALIGN; 122 pte_t pteval = hv_pte_set_ptfn(__pgprot(_PAGE_TABLE), l2_ptfn); 123 BUG_ON((pa & (HV_PAGE_TABLE_ALIGN-1)) != 0); 124 pteval = pte_set_home(pteval, initial_heap_home()); 125 *(pte_t *)pmd = pteval; 126 if (page_table != (pte_t *)pmd_page_vaddr(*pmd)) 127 BUG(); 128} 129 130#ifdef __tilegx__ 131 132static inline pmd_t *alloc_pmd(void) 133{ 134 return __alloc_bootmem(L1_KERNEL_PGTABLE_SIZE, HV_PAGE_TABLE_ALIGN, 0); 135} 136 137static inline void assign_pmd(pud_t *pud, pmd_t *pmd) 138{ 139 assign_pte((pmd_t *)pud, (pte_t *)pmd); 140} 141 142#endif /* __tilegx__ */ 143 144/* Replace the given pmd with a full PTE table. */ 145void __init shatter_pmd(pmd_t *pmd) 146{ 147 pte_t *pte = get_prealloc_pte(pte_pfn(*(pte_t *)pmd)); 148 assign_pte(pmd, pte); 149} 150 151#ifdef __tilegx__ 152static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va) 153{ 154 pud_t *pud = pud_offset(&pgtables[pgd_index(va)], va); 155 if (pud_none(*pud)) 156 assign_pmd(pud, alloc_pmd()); 157 return pmd_offset(pud, va); 158} 159#else 160static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va) 161{ 162 return pmd_offset(pud_offset(&pgtables[pgd_index(va)], va), va); 163} 164#endif 165 166/* 167 * This function initializes a certain range of kernel virtual memory 168 * with new bootmem page tables, everywhere page tables are missing in 169 * the given range. 170 */ 171 172/* 173 * NOTE: The pagetables are allocated contiguous on the physical space 174 * so we can cache the place of the first one and move around without 175 * checking the pgd every time. 176 */ 177static void __init page_table_range_init(unsigned long start, 178 unsigned long end, pgd_t *pgd) 179{ 180 unsigned long vaddr; 181 start = round_down(start, PMD_SIZE); 182 end = round_up(end, PMD_SIZE); 183 for (vaddr = start; vaddr < end; vaddr += PMD_SIZE) { 184 pmd_t *pmd = get_pmd(pgd, vaddr); 185 if (pmd_none(*pmd)) 186 assign_pte(pmd, alloc_pte()); 187 } 188} 189 190 191static int __initdata ktext_hash = 1; /* .text pages */ 192static int __initdata kdata_hash = 1; /* .data and .bss pages */ 193int __write_once hash_default = 1; /* kernel allocator pages */ 194EXPORT_SYMBOL(hash_default); 195int __write_once kstack_hash = 1; /* if no homecaching, use h4h */ 196 197/* 198 * CPUs to use to for striping the pages of kernel data. If hash-for-home 199 * is available, this is only relevant if kcache_hash sets up the 200 * .data and .bss to be page-homed, and we don't want the default mode 201 * of using the full set of kernel cpus for the striping. 202 */ 203static __initdata struct cpumask kdata_mask; 204static __initdata int kdata_arg_seen; 205 206int __write_once kdata_huge; /* if no homecaching, small pages */ 207 208 209/* Combine a generic pgprot_t with cache home to get a cache-aware pgprot. */ 210static pgprot_t __init construct_pgprot(pgprot_t prot, int home) 211{ 212 prot = pte_set_home(prot, home); 213 if (home == PAGE_HOME_IMMUTABLE) { 214 if (ktext_hash) 215 prot = hv_pte_set_mode(prot, HV_PTE_MODE_CACHE_HASH_L3); 216 else 217 prot = hv_pte_set_mode(prot, HV_PTE_MODE_CACHE_NO_L3); 218 } 219 return prot; 220} 221 222/* 223 * For a given kernel data VA, how should it be cached? 224 * We return the complete pgprot_t with caching bits set. 225 */ 226static pgprot_t __init init_pgprot(ulong address) 227{ 228 int cpu; 229 unsigned long page; 230 enum { CODE_DELTA = MEM_SV_START - PAGE_OFFSET }; 231 232 /* For kdata=huge, everything is just hash-for-home. */ 233 if (kdata_huge) 234 return construct_pgprot(PAGE_KERNEL, PAGE_HOME_HASH); 235 236 /* 237 * We map the aliased pages of permanent text so we can 238 * update them if necessary, for ftrace, etc. 239 */ 240 if (address < (ulong) _sinittext - CODE_DELTA) 241 return construct_pgprot(PAGE_KERNEL, PAGE_HOME_HASH); 242 243 /* We map read-only data non-coherent for performance. */ 244 if ((address >= (ulong) __start_rodata && 245 address < (ulong) __end_rodata) || 246 address == (ulong) empty_zero_page) { 247 return construct_pgprot(PAGE_KERNEL_RO, PAGE_HOME_IMMUTABLE); 248 } 249 250#ifndef __tilegx__ 251 /* Force the atomic_locks[] array page to be hash-for-home. */ 252 if (address == (ulong) atomic_locks) 253 return construct_pgprot(PAGE_KERNEL, PAGE_HOME_HASH); 254#endif 255 256 /* 257 * Everything else that isn't data or bss is heap, so mark it 258 * with the initial heap home (hash-for-home, or this cpu). This 259 * includes any addresses after the loaded image and any address before 260 * __init_end, since we already captured the case of text before 261 * _sinittext, and __pa(einittext) is approximately __pa(__init_begin). 262 * 263 * All the LOWMEM pages that we mark this way will get their 264 * struct page homecache properly marked later, in set_page_homes(). 265 * The HIGHMEM pages we leave with a default zero for their 266 * homes, but with a zero free_time we don't have to actually 267 * do a flush action the first time we use them, either. 268 */ 269 if (address >= (ulong) _end || address < (ulong) __init_end) 270 return construct_pgprot(PAGE_KERNEL, initial_heap_home()); 271 272 /* Use hash-for-home if requested for data/bss. */ 273 if (kdata_hash) 274 return construct_pgprot(PAGE_KERNEL, PAGE_HOME_HASH); 275 276 /* 277 * Otherwise we just hand out consecutive cpus. To avoid 278 * requiring this function to hold state, we just walk forward from 279 * __end_rodata by PAGE_SIZE, skipping the readonly and init data, to 280 * reach the requested address, while walking cpu home around 281 * kdata_mask. This is typically no more than a dozen or so iterations. 282 */ 283 page = (((ulong)__end_rodata) + PAGE_SIZE - 1) & PAGE_MASK; 284 BUG_ON(address < page || address >= (ulong)_end); 285 cpu = cpumask_first(&kdata_mask); 286 for (; page < address; page += PAGE_SIZE) { 287 if (page >= (ulong)&init_thread_union && 288 page < (ulong)&init_thread_union + THREAD_SIZE) 289 continue; 290 if (page == (ulong)empty_zero_page) 291 continue; 292#ifndef __tilegx__ 293 if (page == (ulong)atomic_locks) 294 continue; 295#endif 296 cpu = cpumask_next(cpu, &kdata_mask); 297 if (cpu == NR_CPUS) 298 cpu = cpumask_first(&kdata_mask); 299 } 300 return construct_pgprot(PAGE_KERNEL, cpu); 301} 302 303/* 304 * This function sets up how we cache the kernel text. If we have 305 * hash-for-home support, normally that is used instead (see the 306 * kcache_hash boot flag for more information). But if we end up 307 * using a page-based caching technique, this option sets up the 308 * details of that. In addition, the "ktext=nocache" option may 309 * always be used to disable local caching of text pages, if desired. 310 */ 311 312static int __initdata ktext_arg_seen; 313static int __initdata ktext_small; 314static int __initdata ktext_local; 315static int __initdata ktext_all; 316static int __initdata ktext_nondataplane; 317static int __initdata ktext_nocache; 318static struct cpumask __initdata ktext_mask; 319 320static int __init setup_ktext(char *str) 321{ 322 if (str == NULL) 323 return -EINVAL; 324 325 /* If you have a leading "nocache", turn off ktext caching */ 326 if (strncmp(str, "nocache", 7) == 0) { 327 ktext_nocache = 1; 328 pr_info("ktext: disabling local caching of kernel text\n"); 329 str += 7; 330 if (*str == ',') 331 ++str; 332 if (*str == '\0') 333 return 0; 334 } 335 336 ktext_arg_seen = 1; 337 338 /* Default setting: use a huge page */ 339 if (strcmp(str, "huge") == 0) 340 pr_info("ktext: using one huge locally cached page\n"); 341 342 /* Pay TLB cost but get no cache benefit: cache small pages locally */ 343 else if (strcmp(str, "local") == 0) { 344 ktext_small = 1; 345 ktext_local = 1; 346 pr_info("ktext: using small pages with local caching\n"); 347 } 348 349 /* Neighborhood cache ktext pages on all cpus. */ 350 else if (strcmp(str, "all") == 0) { 351 ktext_small = 1; 352 ktext_all = 1; 353 pr_info("ktext: using maximal caching neighborhood\n"); 354 } 355 356 357 /* Neighborhood ktext pages on specified mask */ 358 else if (cpulist_parse(str, &ktext_mask) == 0) { 359 if (cpumask_weight(&ktext_mask) > 1) { 360 ktext_small = 1; 361 pr_info("ktext: using caching neighborhood %*pbl with small pages\n", 362 cpumask_pr_args(&ktext_mask)); 363 } else { 364 pr_info("ktext: caching on cpu %*pbl with one huge page\n", 365 cpumask_pr_args(&ktext_mask)); 366 } 367 } 368 369 else if (*str) 370 return -EINVAL; 371 372 return 0; 373} 374 375early_param("ktext", setup_ktext); 376 377 378static inline pgprot_t ktext_set_nocache(pgprot_t prot) 379{ 380 if (!ktext_nocache) 381 prot = hv_pte_set_nc(prot); 382 else 383 prot = hv_pte_set_no_alloc_l2(prot); 384 return prot; 385} 386 387/* Temporary page table we use for staging. */ 388static pgd_t pgtables[PTRS_PER_PGD] 389 __attribute__((aligned(HV_PAGE_TABLE_ALIGN))); 390 391/* 392 * This maps the physical memory to kernel virtual address space, a total 393 * of max_low_pfn pages, by creating page tables starting from address 394 * PAGE_OFFSET. 395 * 396 * This routine transitions us from using a set of compiled-in large 397 * pages to using some more precise caching, including removing access 398 * to code pages mapped at PAGE_OFFSET (executed only at MEM_SV_START) 399 * marking read-only data as locally cacheable, striping the remaining 400 * .data and .bss across all the available tiles, and removing access 401 * to pages above the top of RAM (thus ensuring a page fault from a bad 402 * virtual address rather than a hypervisor shoot down for accessing 403 * memory outside the assigned limits). 404 */ 405static void __init kernel_physical_mapping_init(pgd_t *pgd_base) 406{ 407 unsigned long long irqmask; 408 unsigned long address, pfn; 409 pmd_t *pmd; 410 pte_t *pte; 411 int pte_ofs; 412 const struct cpumask *my_cpu_mask = cpumask_of(smp_processor_id()); 413 struct cpumask kstripe_mask; 414 int rc, i; 415 416 if (ktext_arg_seen && ktext_hash) { 417 pr_warn("warning: \"ktext\" boot argument ignored if \"kcache_hash\" sets up text hash-for-home\n"); 418 ktext_small = 0; 419 } 420 421 if (kdata_arg_seen && kdata_hash) { 422 pr_warn("warning: \"kdata\" boot argument ignored if \"kcache_hash\" sets up data hash-for-home\n"); 423 } 424 425 if (kdata_huge && !hash_default) { 426 pr_warn("warning: disabling \"kdata=huge\"; requires kcache_hash=all or =allbutstack\n"); 427 kdata_huge = 0; 428 } 429 430 /* 431 * Set up a mask for cpus to use for kernel striping. 432 * This is normally all cpus, but minus dataplane cpus if any. 433 * If the dataplane covers the whole chip, we stripe over 434 * the whole chip too. 435 */ 436 cpumask_copy(&kstripe_mask, cpu_possible_mask); 437 if (!kdata_arg_seen) 438 kdata_mask = kstripe_mask; 439 440 /* Allocate and fill in L2 page tables */ 441 for (i = 0; i < MAX_NUMNODES; ++i) { 442#ifdef CONFIG_HIGHMEM 443 unsigned long end_pfn = node_lowmem_end_pfn[i]; 444#else 445 unsigned long end_pfn = node_end_pfn[i]; 446#endif 447 unsigned long end_huge_pfn = 0; 448 449 /* Pre-shatter the last huge page to allow per-cpu pages. */ 450 if (kdata_huge) 451 end_huge_pfn = end_pfn - (HPAGE_SIZE >> PAGE_SHIFT); 452 453 pfn = node_start_pfn[i]; 454 455 /* Allocate enough memory to hold L2 page tables for node. */ 456 init_prealloc_ptes(i, end_pfn - pfn); 457 458 address = (unsigned long) pfn_to_kaddr(pfn); 459 while (pfn < end_pfn) { 460 BUG_ON(address & (HPAGE_SIZE-1)); 461 pmd = get_pmd(pgtables, address); 462 pte = get_prealloc_pte(pfn); 463 if (pfn < end_huge_pfn) { 464 pgprot_t prot = init_pgprot(address); 465 *(pte_t *)pmd = pte_mkhuge(pfn_pte(pfn, prot)); 466 for (pte_ofs = 0; pte_ofs < PTRS_PER_PTE; 467 pfn++, pte_ofs++, address += PAGE_SIZE) 468 pte[pte_ofs] = pfn_pte(pfn, prot); 469 } else { 470 if (kdata_huge) 471 printk(KERN_DEBUG "pre-shattered huge page at %#lx\n", 472 address); 473 for (pte_ofs = 0; pte_ofs < PTRS_PER_PTE; 474 pfn++, pte_ofs++, address += PAGE_SIZE) { 475 pgprot_t prot = init_pgprot(address); 476 pte[pte_ofs] = pfn_pte(pfn, prot); 477 } 478 assign_pte(pmd, pte); 479 } 480 } 481 } 482 483 /* 484 * Set or check ktext_map now that we have cpu_possible_mask 485 * and kstripe_mask to work with. 486 */ 487 if (ktext_all) 488 cpumask_copy(&ktext_mask, cpu_possible_mask); 489 else if (ktext_nondataplane) 490 ktext_mask = kstripe_mask; 491 else if (!cpumask_empty(&ktext_mask)) { 492 /* Sanity-check any mask that was requested */ 493 struct cpumask bad; 494 cpumask_andnot(&bad, &ktext_mask, cpu_possible_mask); 495 cpumask_and(&ktext_mask, &ktext_mask, cpu_possible_mask); 496 if (!cpumask_empty(&bad)) 497 pr_info("ktext: not using unavailable cpus %*pbl\n", 498 cpumask_pr_args(&bad)); 499 if (cpumask_empty(&ktext_mask)) { 500 pr_warn("ktext: no valid cpus; caching on %d\n", 501 smp_processor_id()); 502 cpumask_copy(&ktext_mask, 503 cpumask_of(smp_processor_id())); 504 } 505 } 506 507 address = MEM_SV_START; 508 pmd = get_pmd(pgtables, address); 509 pfn = 0; /* code starts at PA 0 */ 510 if (ktext_small) { 511 /* Allocate an L2 PTE for the kernel text */ 512 int cpu = 0; 513 pgprot_t prot = construct_pgprot(PAGE_KERNEL_EXEC, 514 PAGE_HOME_IMMUTABLE); 515 516 if (ktext_local) { 517 if (ktext_nocache) 518 prot = hv_pte_set_mode(prot, 519 HV_PTE_MODE_UNCACHED); 520 else 521 prot = hv_pte_set_mode(prot, 522 HV_PTE_MODE_CACHE_NO_L3); 523 } else { 524 prot = hv_pte_set_mode(prot, 525 HV_PTE_MODE_CACHE_TILE_L3); 526 cpu = cpumask_first(&ktext_mask); 527 528 prot = ktext_set_nocache(prot); 529 } 530 531 BUG_ON(address != (unsigned long)_text); 532 pte = NULL; 533 for (; address < (unsigned long)_einittext; 534 pfn++, address += PAGE_SIZE) { 535 pte_ofs = pte_index(address); 536 if (pte_ofs == 0) { 537 if (pte) 538 assign_pte(pmd++, pte); 539 pte = alloc_pte(); 540 } 541 if (!ktext_local) { 542 prot = set_remote_cache_cpu(prot, cpu); 543 cpu = cpumask_next(cpu, &ktext_mask); 544 if (cpu == NR_CPUS) 545 cpu = cpumask_first(&ktext_mask); 546 } 547 pte[pte_ofs] = pfn_pte(pfn, prot); 548 } 549 if (pte) 550 assign_pte(pmd, pte); 551 } else { 552 pte_t pteval = pfn_pte(0, PAGE_KERNEL_EXEC); 553 pteval = pte_mkhuge(pteval); 554 if (ktext_hash) { 555 pteval = hv_pte_set_mode(pteval, 556 HV_PTE_MODE_CACHE_HASH_L3); 557 pteval = ktext_set_nocache(pteval); 558 } else 559 if (cpumask_weight(&ktext_mask) == 1) { 560 pteval = set_remote_cache_cpu(pteval, 561 cpumask_first(&ktext_mask)); 562 pteval = hv_pte_set_mode(pteval, 563 HV_PTE_MODE_CACHE_TILE_L3); 564 pteval = ktext_set_nocache(pteval); 565 } else if (ktext_nocache) 566 pteval = hv_pte_set_mode(pteval, 567 HV_PTE_MODE_UNCACHED); 568 else 569 pteval = hv_pte_set_mode(pteval, 570 HV_PTE_MODE_CACHE_NO_L3); 571 for (; address < (unsigned long)_einittext; 572 pfn += PFN_DOWN(HPAGE_SIZE), address += HPAGE_SIZE) 573 *(pte_t *)(pmd++) = pfn_pte(pfn, pteval); 574 } 575 576 /* Set swapper_pgprot here so it is flushed to memory right away. */ 577 swapper_pgprot = init_pgprot((unsigned long)swapper_pg_dir); 578 579 /* 580 * Since we may be changing the caching of the stack and page 581 * table itself, we invoke an assembly helper to do the 582 * following steps: 583 * 584 * - flush the cache so we start with an empty slate 585 * - install pgtables[] as the real page table 586 * - flush the TLB so the new page table takes effect 587 */ 588 irqmask = interrupt_mask_save_mask(); 589 interrupt_mask_set_mask(-1ULL); 590 rc = flush_and_install_context(__pa(pgtables), 591 init_pgprot((unsigned long)pgtables), 592 __this_cpu_read(current_asid), 593 cpumask_bits(my_cpu_mask)); 594 interrupt_mask_restore_mask(irqmask); 595 BUG_ON(rc != 0); 596 597 /* Copy the page table back to the normal swapper_pg_dir. */ 598 memcpy(pgd_base, pgtables, sizeof(pgtables)); 599 __install_page_table(pgd_base, __this_cpu_read(current_asid), 600 swapper_pgprot); 601 602 /* 603 * We just read swapper_pgprot and thus brought it into the cache, 604 * with its new home & caching mode. When we start the other CPUs, 605 * they're going to reference swapper_pgprot via their initial fake 606 * VA-is-PA mappings, which cache everything locally. At that 607 * time, if it's in our cache with a conflicting home, the 608 * simulator's coherence checker will complain. So, flush it out 609 * of our cache; we're not going to ever use it again anyway. 610 */ 611 __insn_finv(&swapper_pgprot); 612} 613 614/* 615 * devmem_is_allowed() checks to see if /dev/mem access to a certain address 616 * is valid. The argument is a physical page number. 617 * 618 * On Tile, the only valid things for which we can just hand out unchecked 619 * PTEs are the kernel code and data. Anything else might change its 620 * homing with time, and we wouldn't know to adjust the /dev/mem PTEs. 621 * Note that init_thread_union is released to heap soon after boot, 622 * so we include it in the init data. 623 * 624 * For TILE-Gx, we might want to consider allowing access to PA 625 * regions corresponding to PCI space, etc. 626 */ 627int devmem_is_allowed(unsigned long pagenr) 628{ 629 return pagenr < kaddr_to_pfn(_end) && 630 !(pagenr >= kaddr_to_pfn(&init_thread_union) || 631 pagenr < kaddr_to_pfn(__init_end)) && 632 !(pagenr >= kaddr_to_pfn(_sinittext) || 633 pagenr <= kaddr_to_pfn(_einittext-1)); 634} 635 636#ifdef CONFIG_HIGHMEM 637static void __init permanent_kmaps_init(pgd_t *pgd_base) 638{ 639 pgd_t *pgd; 640 pud_t *pud; 641 pmd_t *pmd; 642 pte_t *pte; 643 unsigned long vaddr; 644 645 vaddr = PKMAP_BASE; 646 page_table_range_init(vaddr, vaddr + PAGE_SIZE*LAST_PKMAP, pgd_base); 647 648 pgd = swapper_pg_dir + pgd_index(vaddr); 649 pud = pud_offset(pgd, vaddr); 650 pmd = pmd_offset(pud, vaddr); 651 pte = pte_offset_kernel(pmd, vaddr); 652 pkmap_page_table = pte; 653} 654#endif /* CONFIG_HIGHMEM */ 655 656 657#ifndef CONFIG_64BIT 658static void __init init_free_pfn_range(unsigned long start, unsigned long end) 659{ 660 unsigned long pfn; 661 struct page *page = pfn_to_page(start); 662 663 for (pfn = start; pfn < end; ) { 664 /* Optimize by freeing pages in large batches */ 665 int order = __ffs(pfn); 666 int count, i; 667 struct page *p; 668 669 if (order >= MAX_ORDER) 670 order = MAX_ORDER-1; 671 count = 1 << order; 672 while (pfn + count > end) { 673 count >>= 1; 674 --order; 675 } 676 for (p = page, i = 0; i < count; ++i, ++p) { 677 __ClearPageReserved(p); 678 /* 679 * Hacky direct set to avoid unnecessary 680 * lock take/release for EVERY page here. 681 */ 682 p->_count.counter = 0; 683 p->_mapcount.counter = -1; 684 } 685 init_page_count(page); 686 __free_pages(page, order); 687 adjust_managed_page_count(page, count); 688 689 page += count; 690 pfn += count; 691 } 692} 693 694static void __init set_non_bootmem_pages_init(void) 695{ 696 struct zone *z; 697 for_each_zone(z) { 698 unsigned long start, end; 699 int nid = z->zone_pgdat->node_id; 700#ifdef CONFIG_HIGHMEM 701 int idx = zone_idx(z); 702#endif 703 704 start = z->zone_start_pfn; 705 end = start + z->spanned_pages; 706 start = max(start, node_free_pfn[nid]); 707 start = max(start, max_low_pfn); 708 709#ifdef CONFIG_HIGHMEM 710 if (idx == ZONE_HIGHMEM) 711 totalhigh_pages += z->spanned_pages; 712#endif 713 if (kdata_huge) { 714 unsigned long percpu_pfn = node_percpu_pfn[nid]; 715 if (start < percpu_pfn && end > percpu_pfn) 716 end = percpu_pfn; 717 } 718#ifdef CONFIG_PCI 719 if (start <= pci_reserve_start_pfn && 720 end > pci_reserve_start_pfn) { 721 if (end > pci_reserve_end_pfn) 722 init_free_pfn_range(pci_reserve_end_pfn, end); 723 end = pci_reserve_start_pfn; 724 } 725#endif 726 init_free_pfn_range(start, end); 727 } 728} 729#endif 730 731/* 732 * paging_init() sets up the page tables - note that all of lowmem is 733 * already mapped by head.S. 734 */ 735void __init paging_init(void) 736{ 737#ifdef __tilegx__ 738 pud_t *pud; 739#endif 740 pgd_t *pgd_base = swapper_pg_dir; 741 742 kernel_physical_mapping_init(pgd_base); 743 744 /* Fixed mappings, only the page table structure has to be created. */ 745 page_table_range_init(fix_to_virt(__end_of_fixed_addresses - 1), 746 FIXADDR_TOP, pgd_base); 747 748#ifdef CONFIG_HIGHMEM 749 permanent_kmaps_init(pgd_base); 750#endif 751 752#ifdef __tilegx__ 753 /* 754 * Since GX allocates just one pmd_t array worth of vmalloc space, 755 * we go ahead and allocate it statically here, then share it 756 * globally. As a result we don't have to worry about any task 757 * changing init_mm once we get up and running, and there's no 758 * need for e.g. vmalloc_sync_all(). 759 */ 760 BUILD_BUG_ON(pgd_index(VMALLOC_START) != pgd_index(VMALLOC_END - 1)); 761 pud = pud_offset(pgd_base + pgd_index(VMALLOC_START), VMALLOC_START); 762 assign_pmd(pud, alloc_pmd()); 763#endif 764} 765 766 767/* 768 * Walk the kernel page tables and derive the page_home() from 769 * the PTEs, so that set_pte() can properly validate the caching 770 * of all PTEs it sees. 771 */ 772void __init set_page_homes(void) 773{ 774} 775 776static void __init set_max_mapnr_init(void) 777{ 778#ifdef CONFIG_FLATMEM 779 max_mapnr = max_low_pfn; 780#endif 781} 782 783void __init mem_init(void) 784{ 785 int i; 786#ifndef __tilegx__ 787 void *last; 788#endif 789 790#ifdef CONFIG_FLATMEM 791 BUG_ON(!mem_map); 792#endif 793 794#ifdef CONFIG_HIGHMEM 795 /* check that fixmap and pkmap do not overlap */ 796 if (PKMAP_ADDR(LAST_PKMAP-1) >= FIXADDR_START) { 797 pr_err("fixmap and kmap areas overlap - this will crash\n"); 798 pr_err("pkstart: %lxh pkend: %lxh fixstart %lxh\n", 799 PKMAP_BASE, PKMAP_ADDR(LAST_PKMAP-1), FIXADDR_START); 800 BUG(); 801 } 802#endif 803 804 set_max_mapnr_init(); 805 806 /* this will put all bootmem onto the freelists */ 807 free_all_bootmem(); 808 809#ifndef CONFIG_64BIT 810 /* count all remaining LOWMEM and give all HIGHMEM to page allocator */ 811 set_non_bootmem_pages_init(); 812#endif 813 814 mem_init_print_info(NULL); 815 816 /* 817 * In debug mode, dump some interesting memory mappings. 818 */ 819#ifdef CONFIG_HIGHMEM 820 printk(KERN_DEBUG " KMAP %#lx - %#lx\n", 821 FIXADDR_START, FIXADDR_TOP + PAGE_SIZE - 1); 822 printk(KERN_DEBUG " PKMAP %#lx - %#lx\n", 823 PKMAP_BASE, PKMAP_ADDR(LAST_PKMAP) - 1); 824#endif 825 printk(KERN_DEBUG " VMALLOC %#lx - %#lx\n", 826 _VMALLOC_START, _VMALLOC_END - 1); 827#ifdef __tilegx__ 828 for (i = MAX_NUMNODES-1; i >= 0; --i) { 829 struct pglist_data *node = &node_data[i]; 830 if (node->node_present_pages) { 831 unsigned long start = (unsigned long) 832 pfn_to_kaddr(node->node_start_pfn); 833 unsigned long end = start + 834 (node->node_present_pages << PAGE_SHIFT); 835 printk(KERN_DEBUG " MEM%d %#lx - %#lx\n", 836 i, start, end - 1); 837 } 838 } 839#else 840 last = high_memory; 841 for (i = MAX_NUMNODES-1; i >= 0; --i) { 842 if ((unsigned long)vbase_map[i] != -1UL) { 843 printk(KERN_DEBUG " LOWMEM%d %#lx - %#lx\n", 844 i, (unsigned long) (vbase_map[i]), 845 (unsigned long) (last-1)); 846 last = vbase_map[i]; 847 } 848 } 849#endif 850 851#ifndef __tilegx__ 852 /* 853 * Convert from using one lock for all atomic operations to 854 * one per cpu. 855 */ 856 __init_atomic_per_cpu(); 857#endif 858} 859 860/* 861 * this is for the non-NUMA, single node SMP system case. 862 * Specifically, in the case of x86, we will always add 863 * memory to the highmem for now. 864 */ 865#ifndef CONFIG_NEED_MULTIPLE_NODES 866int arch_add_memory(u64 start, u64 size) 867{ 868 struct pglist_data *pgdata = &contig_page_data; 869 struct zone *zone = pgdata->node_zones + MAX_NR_ZONES-1; 870 unsigned long start_pfn = start >> PAGE_SHIFT; 871 unsigned long nr_pages = size >> PAGE_SHIFT; 872 873 return __add_pages(zone, start_pfn, nr_pages); 874} 875 876int remove_memory(u64 start, u64 size) 877{ 878 return -EINVAL; 879} 880 881#ifdef CONFIG_MEMORY_HOTREMOVE 882int arch_remove_memory(u64 start, u64 size) 883{ 884 /* TODO */ 885 return -EBUSY; 886} 887#endif 888#endif 889 890struct kmem_cache *pgd_cache; 891 892void __init pgtable_cache_init(void) 893{ 894 pgd_cache = kmem_cache_create("pgd", SIZEOF_PGD, SIZEOF_PGD, 0, NULL); 895 if (!pgd_cache) 896 panic("pgtable_cache_init(): Cannot create pgd cache"); 897} 898 899#ifdef CONFIG_DEBUG_PAGEALLOC 900static long __write_once initfree; 901#else 902static long __write_once initfree = 1; 903#endif 904 905/* Select whether to free (1) or mark unusable (0) the __init pages. */ 906static int __init set_initfree(char *str) 907{ 908 long val; 909 if (kstrtol(str, 0, &val) == 0) { 910 initfree = val; 911 pr_info("initfree: %s free init pages\n", 912 initfree ? "will" : "won't"); 913 } 914 return 1; 915} 916__setup("initfree=", set_initfree); 917 918static void free_init_pages(char *what, unsigned long begin, unsigned long end) 919{ 920 unsigned long addr = (unsigned long) begin; 921 922 if (kdata_huge && !initfree) { 923 pr_warn("Warning: ignoring initfree=0: incompatible with kdata=huge\n"); 924 initfree = 1; 925 } 926 end = (end + PAGE_SIZE - 1) & PAGE_MASK; 927 local_flush_tlb_pages(NULL, begin, PAGE_SIZE, end - begin); 928 for (addr = begin; addr < end; addr += PAGE_SIZE) { 929 /* 930 * Note we just reset the home here directly in the 931 * page table. We know this is safe because our caller 932 * just flushed the caches on all the other cpus, 933 * and they won't be touching any of these pages. 934 */ 935 int pfn = kaddr_to_pfn((void *)addr); 936 struct page *page = pfn_to_page(pfn); 937 pte_t *ptep = virt_to_kpte(addr); 938 if (!initfree) { 939 /* 940 * If debugging page accesses then do not free 941 * this memory but mark them not present - any 942 * buggy init-section access will create a 943 * kernel page fault: 944 */ 945 pte_clear(&init_mm, addr, ptep); 946 continue; 947 } 948 if (pte_huge(*ptep)) 949 BUG_ON(!kdata_huge); 950 else 951 set_pte_at(&init_mm, addr, ptep, 952 pfn_pte(pfn, PAGE_KERNEL)); 953 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE); 954 free_reserved_page(page); 955 } 956 pr_info("Freeing %s: %ldk freed\n", what, (end - begin) >> 10); 957} 958 959void free_initmem(void) 960{ 961 const unsigned long text_delta = MEM_SV_START - PAGE_OFFSET; 962 963 /* 964 * Evict the cache on all cores to avoid incoherence. 965 * We are guaranteed that no one will touch the init pages any more. 966 */ 967 homecache_evict(&cpu_cacheable_map); 968 969 /* Free the data pages that we won't use again after init. */ 970 free_init_pages("unused kernel data", 971 (unsigned long)__init_begin, 972 (unsigned long)__init_end); 973 974 /* 975 * Free the pages mapped from 0xc0000000 that correspond to code 976 * pages from MEM_SV_START that we won't use again after init. 977 */ 978 free_init_pages("unused kernel text", 979 (unsigned long)_sinittext - text_delta, 980 (unsigned long)_einittext - text_delta); 981 /* Do a global TLB flush so everyone sees the changes. */ 982 flush_tlb_all(); 983} 984