1/* 2 * pcic.c: MicroSPARC-IIep PCI controller support 3 * 4 * Copyright (C) 1998 V. Roganov and G. Raiko 5 * 6 * Code is derived from Ultra/PCI PSYCHO controller support, see that 7 * for author info. 8 * 9 * Support for diverse IIep based platforms by Pete Zaitcev. 10 * CP-1200 by Eric Brower. 11 */ 12 13#include <linux/kernel.h> 14#include <linux/types.h> 15#include <linux/init.h> 16#include <linux/mm.h> 17#include <linux/slab.h> 18#include <linux/jiffies.h> 19 20#include <asm/swift.h> /* for cache flushing. */ 21#include <asm/io.h> 22 23#include <linux/ctype.h> 24#include <linux/pci.h> 25#include <linux/time.h> 26#include <linux/timex.h> 27#include <linux/interrupt.h> 28#include <linux/export.h> 29 30#include <asm/irq.h> 31#include <asm/oplib.h> 32#include <asm/prom.h> 33#include <asm/pcic.h> 34#include <asm/timex.h> 35#include <asm/timer.h> 36#include <asm/uaccess.h> 37#include <asm/irq_regs.h> 38 39#include "kernel.h" 40#include "irq.h" 41 42/* 43 * I studied different documents and many live PROMs both from 2.30 44 * family and 3.xx versions. I came to the amazing conclusion: there is 45 * absolutely no way to route interrupts in IIep systems relying on 46 * information which PROM presents. We must hardcode interrupt routing 47 * schematics. And this actually sucks. -- zaitcev 1999/05/12 48 * 49 * To find irq for a device we determine which routing map 50 * is in effect or, in other words, on which machine we are running. 51 * We use PROM name for this although other techniques may be used 52 * in special cases (Gleb reports a PROMless IIep based system). 53 * Once we know the map we take device configuration address and 54 * find PCIC pin number where INT line goes. Then we may either program 55 * preferred irq into the PCIC or supply the preexisting irq to the device. 56 */ 57struct pcic_ca2irq { 58 unsigned char busno; /* PCI bus number */ 59 unsigned char devfn; /* Configuration address */ 60 unsigned char pin; /* PCIC external interrupt pin */ 61 unsigned char irq; /* Preferred IRQ (mappable in PCIC) */ 62 unsigned int force; /* Enforce preferred IRQ */ 63}; 64 65struct pcic_sn2list { 66 char *sysname; 67 struct pcic_ca2irq *intmap; 68 int mapdim; 69}; 70 71/* 72 * JavaEngine-1 apparently has different versions. 73 * 74 * According to communications with Sun folks, for P2 build 501-4628-03: 75 * pin 0 - parallel, audio; 76 * pin 1 - Ethernet; 77 * pin 2 - su; 78 * pin 3 - PS/2 kbd and mouse. 79 * 80 * OEM manual (805-1486): 81 * pin 0: Ethernet 82 * pin 1: All EBus 83 * pin 2: IGA (unused) 84 * pin 3: Not connected 85 * OEM manual says that 501-4628 & 501-4811 are the same thing, 86 * only the latter has NAND flash in place. 87 * 88 * So far unofficial Sun wins over the OEM manual. Poor OEMs... 89 */ 90static struct pcic_ca2irq pcic_i_je1a[] = { /* 501-4811-03 */ 91 { 0, 0x00, 2, 12, 0 }, /* EBus: hogs all */ 92 { 0, 0x01, 1, 6, 1 }, /* Happy Meal */ 93 { 0, 0x80, 0, 7, 0 }, /* IGA (unused) */ 94}; 95 96/* XXX JS-E entry is incomplete - PCI Slot 2 address (pin 7)? */ 97static struct pcic_ca2irq pcic_i_jse[] = { 98 { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */ 99 { 0, 0x01, 1, 6, 0 }, /* hme */ 100 { 0, 0x08, 2, 9, 0 }, /* VGA - we hope not used :) */ 101 { 0, 0x10, 6, 8, 0 }, /* PCI INTA# in Slot 1 */ 102 { 0, 0x18, 7, 12, 0 }, /* PCI INTA# in Slot 2, shared w. RTC */ 103 { 0, 0x38, 4, 9, 0 }, /* All ISA devices. Read 8259. */ 104 { 0, 0x80, 5, 11, 0 }, /* EIDE */ 105 /* {0,0x88, 0,0,0} - unknown device... PMU? Probably no interrupt. */ 106 { 0, 0xA0, 4, 9, 0 }, /* USB */ 107 /* 108 * Some pins belong to non-PCI devices, we hardcode them in drivers. 109 * sun4m timers - irq 10, 14 110 * PC style RTC - pin 7, irq 4 ? 111 * Smart card, Parallel - pin 4 shared with USB, ISA 112 * audio - pin 3, irq 5 ? 113 */ 114}; 115 116/* SPARCengine-6 was the original release name of CP1200. 117 * The documentation differs between the two versions 118 */ 119static struct pcic_ca2irq pcic_i_se6[] = { 120 { 0, 0x08, 0, 2, 0 }, /* SCSI */ 121 { 0, 0x01, 1, 6, 0 }, /* HME */ 122 { 0, 0x00, 3, 13, 0 }, /* EBus */ 123}; 124 125/* 126 * Krups (courtesy of Varol Kaptan) 127 * No documentation available, but it was easy to guess 128 * because it was very similar to Espresso. 129 * 130 * pin 0 - kbd, mouse, serial; 131 * pin 1 - Ethernet; 132 * pin 2 - igs (we do not use it); 133 * pin 3 - audio; 134 * pin 4,5,6 - unused; 135 * pin 7 - RTC (from P2 onwards as David B. says). 136 */ 137static struct pcic_ca2irq pcic_i_jk[] = { 138 { 0, 0x00, 0, 13, 0 }, /* Ebus - serial and keyboard */ 139 { 0, 0x01, 1, 6, 0 }, /* hme */ 140}; 141 142/* 143 * Several entries in this list may point to the same routing map 144 * as several PROMs may be installed on the same physical board. 145 */ 146#define SN2L_INIT(name, map) \ 147 { name, map, ARRAY_SIZE(map) } 148 149static struct pcic_sn2list pcic_known_sysnames[] = { 150 SN2L_INIT("SUNW,JavaEngine1", pcic_i_je1a), /* JE1, PROM 2.32 */ 151 SN2L_INIT("SUNW,JS-E", pcic_i_jse), /* PROLL JavaStation-E */ 152 SN2L_INIT("SUNW,SPARCengine-6", pcic_i_se6), /* SPARCengine-6/CP-1200 */ 153 SN2L_INIT("SUNW,JS-NC", pcic_i_jk), /* PROLL JavaStation-NC */ 154 SN2L_INIT("SUNW,JSIIep", pcic_i_jk), /* OBP JavaStation-NC */ 155 { NULL, NULL, 0 } 156}; 157 158/* 159 * Only one PCIC per IIep, 160 * and since we have no SMP IIep, only one per system. 161 */ 162static int pcic0_up; 163static struct linux_pcic pcic0; 164 165void __iomem *pcic_regs; 166static volatile int pcic_speculative; 167static volatile int pcic_trapped; 168 169/* forward */ 170unsigned int pcic_build_device_irq(struct platform_device *op, 171 unsigned int real_irq); 172 173#define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (((unsigned int)bus) << 16) | (((unsigned int)device_fn) << 8) | (where & ~3)) 174 175static int pcic_read_config_dword(unsigned int busno, unsigned int devfn, 176 int where, u32 *value) 177{ 178 struct linux_pcic *pcic; 179 unsigned long flags; 180 181 pcic = &pcic0; 182 183 local_irq_save(flags); 184#if 0 /* does not fail here */ 185 pcic_speculative = 1; 186 pcic_trapped = 0; 187#endif 188 writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr); 189#if 0 /* does not fail here */ 190 nop(); 191 if (pcic_trapped) { 192 local_irq_restore(flags); 193 *value = ~0; 194 return 0; 195 } 196#endif 197 pcic_speculative = 2; 198 pcic_trapped = 0; 199 *value = readl(pcic->pcic_config_space_data + (where&4)); 200 nop(); 201 if (pcic_trapped) { 202 pcic_speculative = 0; 203 local_irq_restore(flags); 204 *value = ~0; 205 return 0; 206 } 207 pcic_speculative = 0; 208 local_irq_restore(flags); 209 return 0; 210} 211 212static int pcic_read_config(struct pci_bus *bus, unsigned int devfn, 213 int where, int size, u32 *val) 214{ 215 unsigned int v; 216 217 if (bus->number != 0) return -EINVAL; 218 switch (size) { 219 case 1: 220 pcic_read_config_dword(bus->number, devfn, where&~3, &v); 221 *val = 0xff & (v >> (8*(where & 3))); 222 return 0; 223 case 2: 224 if (where&1) return -EINVAL; 225 pcic_read_config_dword(bus->number, devfn, where&~3, &v); 226 *val = 0xffff & (v >> (8*(where & 3))); 227 return 0; 228 case 4: 229 if (where&3) return -EINVAL; 230 pcic_read_config_dword(bus->number, devfn, where&~3, val); 231 return 0; 232 } 233 return -EINVAL; 234} 235 236static int pcic_write_config_dword(unsigned int busno, unsigned int devfn, 237 int where, u32 value) 238{ 239 struct linux_pcic *pcic; 240 unsigned long flags; 241 242 pcic = &pcic0; 243 244 local_irq_save(flags); 245 writel(CONFIG_CMD(busno, devfn, where), pcic->pcic_config_space_addr); 246 writel(value, pcic->pcic_config_space_data + (where&4)); 247 local_irq_restore(flags); 248 return 0; 249} 250 251static int pcic_write_config(struct pci_bus *bus, unsigned int devfn, 252 int where, int size, u32 val) 253{ 254 unsigned int v; 255 256 if (bus->number != 0) return -EINVAL; 257 switch (size) { 258 case 1: 259 pcic_read_config_dword(bus->number, devfn, where&~3, &v); 260 v = (v & ~(0xff << (8*(where&3)))) | 261 ((0xff&val) << (8*(where&3))); 262 return pcic_write_config_dword(bus->number, devfn, where&~3, v); 263 case 2: 264 if (where&1) return -EINVAL; 265 pcic_read_config_dword(bus->number, devfn, where&~3, &v); 266 v = (v & ~(0xffff << (8*(where&3)))) | 267 ((0xffff&val) << (8*(where&3))); 268 return pcic_write_config_dword(bus->number, devfn, where&~3, v); 269 case 4: 270 if (where&3) return -EINVAL; 271 return pcic_write_config_dword(bus->number, devfn, where, val); 272 } 273 return -EINVAL; 274} 275 276static struct pci_ops pcic_ops = { 277 .read = pcic_read_config, 278 .write = pcic_write_config, 279}; 280 281/* 282 * On sparc64 pcibios_init() calls pci_controller_probe(). 283 * We want PCIC probed little ahead so that interrupt controller 284 * would be operational. 285 */ 286int __init pcic_probe(void) 287{ 288 struct linux_pcic *pcic; 289 struct linux_prom_registers regs[PROMREG_MAX]; 290 struct linux_pbm_info* pbm; 291 char namebuf[64]; 292 phandle node; 293 int err; 294 295 if (pcic0_up) { 296 prom_printf("PCIC: called twice!\n"); 297 prom_halt(); 298 } 299 pcic = &pcic0; 300 301 node = prom_getchild (prom_root_node); 302 node = prom_searchsiblings (node, "pci"); 303 if (node == 0) 304 return -ENODEV; 305 /* 306 * Map in PCIC register set, config space, and IO base 307 */ 308 err = prom_getproperty(node, "reg", (char*)regs, sizeof(regs)); 309 if (err == 0 || err == -1) { 310 prom_printf("PCIC: Error, cannot get PCIC registers " 311 "from PROM.\n"); 312 prom_halt(); 313 } 314 315 pcic0_up = 1; 316 317 pcic->pcic_res_regs.name = "pcic_registers"; 318 pcic->pcic_regs = ioremap(regs[0].phys_addr, regs[0].reg_size); 319 if (!pcic->pcic_regs) { 320 prom_printf("PCIC: Error, cannot map PCIC registers.\n"); 321 prom_halt(); 322 } 323 324 pcic->pcic_res_io.name = "pcic_io"; 325 if ((pcic->pcic_io = (unsigned long) 326 ioremap(regs[1].phys_addr, 0x10000)) == 0) { 327 prom_printf("PCIC: Error, cannot map PCIC IO Base.\n"); 328 prom_halt(); 329 } 330 331 pcic->pcic_res_cfg_addr.name = "pcic_cfg_addr"; 332 if ((pcic->pcic_config_space_addr = 333 ioremap(regs[2].phys_addr, regs[2].reg_size * 2)) == NULL) { 334 prom_printf("PCIC: Error, cannot map " 335 "PCI Configuration Space Address.\n"); 336 prom_halt(); 337 } 338 339 /* 340 * Docs say three least significant bits in address and data 341 * must be the same. Thus, we need adjust size of data. 342 */ 343 pcic->pcic_res_cfg_data.name = "pcic_cfg_data"; 344 if ((pcic->pcic_config_space_data = 345 ioremap(regs[3].phys_addr, regs[3].reg_size * 2)) == NULL) { 346 prom_printf("PCIC: Error, cannot map " 347 "PCI Configuration Space Data.\n"); 348 prom_halt(); 349 } 350 351 pbm = &pcic->pbm; 352 pbm->prom_node = node; 353 prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0; 354 strcpy(pbm->prom_name, namebuf); 355 356 { 357 extern int pcic_nmi_trap_patch[4]; 358 359 t_nmi[0] = pcic_nmi_trap_patch[0]; 360 t_nmi[1] = pcic_nmi_trap_patch[1]; 361 t_nmi[2] = pcic_nmi_trap_patch[2]; 362 t_nmi[3] = pcic_nmi_trap_patch[3]; 363 swift_flush_dcache(); 364 pcic_regs = pcic->pcic_regs; 365 } 366 367 prom_getstring(prom_root_node, "name", namebuf, 63); namebuf[63] = 0; 368 { 369 struct pcic_sn2list *p; 370 371 for (p = pcic_known_sysnames; p->sysname != NULL; p++) { 372 if (strcmp(namebuf, p->sysname) == 0) 373 break; 374 } 375 pcic->pcic_imap = p->intmap; 376 pcic->pcic_imdim = p->mapdim; 377 } 378 if (pcic->pcic_imap == NULL) { 379 /* 380 * We do not panic here for the sake of embedded systems. 381 */ 382 printk("PCIC: System %s is unknown, cannot route interrupts\n", 383 namebuf); 384 } 385 386 return 0; 387} 388 389static void __init pcic_pbm_scan_bus(struct linux_pcic *pcic) 390{ 391 struct linux_pbm_info *pbm = &pcic->pbm; 392 393 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, &pcic_ops, pbm); 394 if (!pbm->pci_bus) 395 return; 396 397#if 0 /* deadwood transplanted from sparc64 */ 398 pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node); 399 pci_record_assignments(pbm, pbm->pci_bus); 400 pci_assign_unassigned(pbm, pbm->pci_bus); 401 pci_fixup_irq(pbm, pbm->pci_bus); 402#endif 403 pci_bus_add_devices(pbm->pci_bus); 404} 405 406/* 407 * Main entry point from the PCI subsystem. 408 */ 409static int __init pcic_init(void) 410{ 411 struct linux_pcic *pcic; 412 413 /* 414 * PCIC should be initialized at start of the timer. 415 * So, here we report the presence of PCIC and do some magic passes. 416 */ 417 if(!pcic0_up) 418 return 0; 419 pcic = &pcic0; 420 421 /* 422 * Switch off IOTLB translation. 423 */ 424 writeb(PCI_DVMA_CONTROL_IOTLB_DISABLE, 425 pcic->pcic_regs+PCI_DVMA_CONTROL); 426 427 /* 428 * Increase mapped size for PCI memory space (DMA access). 429 * Should be done in that order (size first, address second). 430 * Why we couldn't set up 4GB and forget about it? XXX 431 */ 432 writel(0xF0000000UL, pcic->pcic_regs+PCI_SIZE_0); 433 writel(0+PCI_BASE_ADDRESS_SPACE_MEMORY, 434 pcic->pcic_regs+PCI_BASE_ADDRESS_0); 435 436 pcic_pbm_scan_bus(pcic); 437 438 return 0; 439} 440 441int pcic_present(void) 442{ 443 return pcic0_up; 444} 445 446static int pdev_to_pnode(struct linux_pbm_info *pbm, struct pci_dev *pdev) 447{ 448 struct linux_prom_pci_registers regs[PROMREG_MAX]; 449 int err; 450 phandle node = prom_getchild(pbm->prom_node); 451 452 while(node) { 453 err = prom_getproperty(node, "reg", 454 (char *)®s[0], sizeof(regs)); 455 if(err != 0 && err != -1) { 456 unsigned long devfn = (regs[0].which_io >> 8) & 0xff; 457 if(devfn == pdev->devfn) 458 return node; 459 } 460 node = prom_getsibling(node); 461 } 462 return 0; 463} 464 465static inline struct pcidev_cookie *pci_devcookie_alloc(void) 466{ 467 return kmalloc(sizeof(struct pcidev_cookie), GFP_ATOMIC); 468} 469 470static void pcic_map_pci_device(struct linux_pcic *pcic, 471 struct pci_dev *dev, int node) 472{ 473 char namebuf[64]; 474 unsigned long address; 475 unsigned long flags; 476 int j; 477 478 if (node == 0 || node == -1) { 479 strcpy(namebuf, "???"); 480 } else { 481 prom_getstring(node, "name", namebuf, 63); namebuf[63] = 0; 482 } 483 484 for (j = 0; j < 6; j++) { 485 address = dev->resource[j].start; 486 if (address == 0) break; /* are sequential */ 487 flags = dev->resource[j].flags; 488 if ((flags & IORESOURCE_IO) != 0) { 489 if (address < 0x10000) { 490 /* 491 * A device responds to I/O cycles on PCI. 492 * We generate these cycles with memory 493 * access into the fixed map (phys 0x30000000). 494 * 495 * Since a device driver does not want to 496 * do ioremap() before accessing PC-style I/O, 497 * we supply virtual, ready to access address. 498 * 499 * Note that request_region() 500 * works for these devices. 501 * 502 * XXX Neat trick, but it's a *bad* idea 503 * to shit into regions like that. 504 * What if we want to allocate one more 505 * PCI base address... 506 */ 507 dev->resource[j].start = 508 pcic->pcic_io + address; 509 dev->resource[j].end = 1; /* XXX */ 510 dev->resource[j].flags = 511 (flags & ~IORESOURCE_IO) | IORESOURCE_MEM; 512 } else { 513 /* 514 * OOPS... PCI Spec allows this. Sun does 515 * not have any devices getting above 64K 516 * so it must be user with a weird I/O 517 * board in a PCI slot. We must remap it 518 * under 64K but it is not done yet. XXX 519 */ 520 printk("PCIC: Skipping I/O space at 0x%lx, " 521 "this will Oops if a driver attaches " 522 "device '%s' at %02x:%02x)\n", address, 523 namebuf, dev->bus->number, dev->devfn); 524 } 525 } 526 } 527} 528 529static void 530pcic_fill_irq(struct linux_pcic *pcic, struct pci_dev *dev, int node) 531{ 532 struct pcic_ca2irq *p; 533 unsigned int real_irq; 534 int i, ivec; 535 char namebuf[64]; 536 537 if (node == 0 || node == -1) { 538 strcpy(namebuf, "???"); 539 } else { 540 prom_getstring(node, "name", namebuf, sizeof(namebuf)); 541 } 542 543 if ((p = pcic->pcic_imap) == NULL) { 544 dev->irq = 0; 545 return; 546 } 547 for (i = 0; i < pcic->pcic_imdim; i++) { 548 if (p->busno == dev->bus->number && p->devfn == dev->devfn) 549 break; 550 p++; 551 } 552 if (i >= pcic->pcic_imdim) { 553 printk("PCIC: device %s devfn %02x:%02x not found in %d\n", 554 namebuf, dev->bus->number, dev->devfn, pcic->pcic_imdim); 555 dev->irq = 0; 556 return; 557 } 558 559 i = p->pin; 560 if (i >= 0 && i < 4) { 561 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO); 562 real_irq = ivec >> (i << 2) & 0xF; 563 } else if (i >= 4 && i < 8) { 564 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI); 565 real_irq = ivec >> ((i-4) << 2) & 0xF; 566 } else { /* Corrupted map */ 567 printk("PCIC: BAD PIN %d\n", i); for (;;) {} 568 } 569/* P3 */ /* printk("PCIC: device %s pin %d ivec 0x%x irq %x\n", namebuf, i, ivec, dev->irq); */ 570 571 /* real_irq means PROM did not bother to program the upper 572 * half of PCIC. This happens on JS-E with PROM 3.11, for instance. 573 */ 574 if (real_irq == 0 || p->force) { 575 if (p->irq == 0 || p->irq >= 15) { /* Corrupted map */ 576 printk("PCIC: BAD IRQ %d\n", p->irq); for (;;) {} 577 } 578 printk("PCIC: setting irq %d at pin %d for device %02x:%02x\n", 579 p->irq, p->pin, dev->bus->number, dev->devfn); 580 real_irq = p->irq; 581 582 i = p->pin; 583 if (i >= 4) { 584 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI); 585 ivec &= ~(0xF << ((i - 4) << 2)); 586 ivec |= p->irq << ((i - 4) << 2); 587 writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_HI); 588 } else { 589 ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO); 590 ivec &= ~(0xF << (i << 2)); 591 ivec |= p->irq << (i << 2); 592 writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_LO); 593 } 594 } 595 dev->irq = pcic_build_device_irq(NULL, real_irq); 596} 597 598/* 599 * Normally called from {do_}pci_scan_bus... 600 */ 601void pcibios_fixup_bus(struct pci_bus *bus) 602{ 603 struct pci_dev *dev; 604 int i, has_io, has_mem; 605 unsigned int cmd; 606 struct linux_pcic *pcic; 607 /* struct linux_pbm_info* pbm = &pcic->pbm; */ 608 int node; 609 struct pcidev_cookie *pcp; 610 611 if (!pcic0_up) { 612 printk("pcibios_fixup_bus: no PCIC\n"); 613 return; 614 } 615 pcic = &pcic0; 616 617 /* 618 * Next crud is an equivalent of pbm = pcic_bus_to_pbm(bus); 619 */ 620 if (bus->number != 0) { 621 printk("pcibios_fixup_bus: nonzero bus 0x%x\n", bus->number); 622 return; 623 } 624 625 list_for_each_entry(dev, &bus->devices, bus_list) { 626 627 /* 628 * Comment from i386 branch: 629 * There are buggy BIOSes that forget to enable I/O and memory 630 * access to PCI devices. We try to fix this, but we need to 631 * be sure that the BIOS didn't forget to assign an address 632 * to the device. [mj] 633 * OBP is a case of such BIOS :-) 634 */ 635 has_io = has_mem = 0; 636 for(i=0; i<6; i++) { 637 unsigned long f = dev->resource[i].flags; 638 if (f & IORESOURCE_IO) { 639 has_io = 1; 640 } else if (f & IORESOURCE_MEM) 641 has_mem = 1; 642 } 643 pcic_read_config(dev->bus, dev->devfn, PCI_COMMAND, 2, &cmd); 644 if (has_io && !(cmd & PCI_COMMAND_IO)) { 645 printk("PCIC: Enabling I/O for device %02x:%02x\n", 646 dev->bus->number, dev->devfn); 647 cmd |= PCI_COMMAND_IO; 648 pcic_write_config(dev->bus, dev->devfn, 649 PCI_COMMAND, 2, cmd); 650 } 651 if (has_mem && !(cmd & PCI_COMMAND_MEMORY)) { 652 printk("PCIC: Enabling memory for device %02x:%02x\n", 653 dev->bus->number, dev->devfn); 654 cmd |= PCI_COMMAND_MEMORY; 655 pcic_write_config(dev->bus, dev->devfn, 656 PCI_COMMAND, 2, cmd); 657 } 658 659 node = pdev_to_pnode(&pcic->pbm, dev); 660 if(node == 0) 661 node = -1; 662 663 /* cookies */ 664 pcp = pci_devcookie_alloc(); 665 pcp->pbm = &pcic->pbm; 666 pcp->prom_node = of_find_node_by_phandle(node); 667 dev->sysdata = pcp; 668 669 /* fixing I/O to look like memory */ 670 if ((dev->class>>16) != PCI_BASE_CLASS_BRIDGE) 671 pcic_map_pci_device(pcic, dev, node); 672 673 pcic_fill_irq(pcic, dev, node); 674 } 675} 676 677/* Makes compiler happy */ 678static volatile int pcic_timer_dummy; 679 680static void pcic_clear_clock_irq(void) 681{ 682 pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT); 683} 684 685/* CPU frequency is 100 MHz, timer increments every 4 CPU clocks */ 686#define USECS_PER_JIFFY (1000000 / HZ) 687#define TICK_TIMER_LIMIT ((100 * 1000000 / 4) / HZ) 688 689static unsigned int pcic_cycles_offset(void) 690{ 691 u32 value, count; 692 693 value = readl(pcic0.pcic_regs + PCI_SYS_COUNTER); 694 count = value & ~PCI_SYS_COUNTER_OVERFLOW; 695 696 if (value & PCI_SYS_COUNTER_OVERFLOW) 697 count += TICK_TIMER_LIMIT; 698 /* 699 * We divide all by HZ 700 * to have microsecond resolution and to avoid overflow 701 */ 702 count = ((count / HZ) * USECS_PER_JIFFY) / (TICK_TIMER_LIMIT / HZ); 703 704 /* Coordinate with the sparc_config.clock_rate setting */ 705 return count * 2; 706} 707 708void __init pci_time_init(void) 709{ 710 struct linux_pcic *pcic = &pcic0; 711 unsigned long v; 712 int timer_irq, irq; 713 int err; 714 715#ifndef CONFIG_SMP 716 /* 717 * The clock_rate is in SBUS dimension. 718 * We take into account this in pcic_cycles_offset() 719 */ 720 sparc_config.clock_rate = SBUS_CLOCK_RATE / HZ; 721 sparc_config.features |= FEAT_L10_CLOCKEVENT; 722#endif 723 sparc_config.features |= FEAT_L10_CLOCKSOURCE; 724 sparc_config.get_cycles_offset = pcic_cycles_offset; 725 726 writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT); 727 /* PROM should set appropriate irq */ 728 v = readb(pcic->pcic_regs+PCI_COUNTER_IRQ); 729 timer_irq = PCI_COUNTER_IRQ_SYS(v); 730 writel (PCI_COUNTER_IRQ_SET(timer_irq, 0), 731 pcic->pcic_regs+PCI_COUNTER_IRQ); 732 irq = pcic_build_device_irq(NULL, timer_irq); 733 err = request_irq(irq, timer_interrupt, 734 IRQF_TIMER, "timer", NULL); 735 if (err) { 736 prom_printf("time_init: unable to attach IRQ%d\n", timer_irq); 737 prom_halt(); 738 } 739 local_irq_enable(); 740} 741 742 743#if 0 744static void watchdog_reset() { 745 writeb(0, pcic->pcic_regs+PCI_SYS_STATUS); 746} 747#endif 748 749resource_size_t pcibios_align_resource(void *data, const struct resource *res, 750 resource_size_t size, resource_size_t align) 751{ 752 return res->start; 753} 754 755int pcibios_enable_device(struct pci_dev *pdev, int mask) 756{ 757 return 0; 758} 759 760/* 761 * NMI 762 */ 763void pcic_nmi(unsigned int pend, struct pt_regs *regs) 764{ 765 766 pend = swab32(pend); 767 768 if (!pcic_speculative || (pend & PCI_SYS_INT_PENDING_PIO) == 0) { 769 /* 770 * XXX On CP-1200 PCI #SERR may happen, we do not know 771 * what to do about it yet. 772 */ 773 printk("Aiee, NMI pend 0x%x pc 0x%x spec %d, hanging\n", 774 pend, (int)regs->pc, pcic_speculative); 775 for (;;) { } 776 } 777 pcic_speculative = 0; 778 pcic_trapped = 1; 779 regs->pc = regs->npc; 780 regs->npc += 4; 781} 782 783static inline unsigned long get_irqmask(int irq_nr) 784{ 785 return 1 << irq_nr; 786} 787 788static void pcic_mask_irq(struct irq_data *data) 789{ 790 unsigned long mask, flags; 791 792 mask = (unsigned long)data->chip_data; 793 local_irq_save(flags); 794 writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET); 795 local_irq_restore(flags); 796} 797 798static void pcic_unmask_irq(struct irq_data *data) 799{ 800 unsigned long mask, flags; 801 802 mask = (unsigned long)data->chip_data; 803 local_irq_save(flags); 804 writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR); 805 local_irq_restore(flags); 806} 807 808static unsigned int pcic_startup_irq(struct irq_data *data) 809{ 810 irq_link(data->irq); 811 pcic_unmask_irq(data); 812 return 0; 813} 814 815static struct irq_chip pcic_irq = { 816 .name = "pcic", 817 .irq_startup = pcic_startup_irq, 818 .irq_mask = pcic_mask_irq, 819 .irq_unmask = pcic_unmask_irq, 820}; 821 822unsigned int pcic_build_device_irq(struct platform_device *op, 823 unsigned int real_irq) 824{ 825 unsigned int irq; 826 unsigned long mask; 827 828 irq = 0; 829 mask = get_irqmask(real_irq); 830 if (mask == 0) 831 goto out; 832 833 irq = irq_alloc(real_irq, real_irq); 834 if (irq == 0) 835 goto out; 836 837 irq_set_chip_and_handler_name(irq, &pcic_irq, 838 handle_level_irq, "PCIC"); 839 irq_set_chip_data(irq, (void *)mask); 840 841out: 842 return irq; 843} 844 845 846static void pcic_load_profile_irq(int cpu, unsigned int limit) 847{ 848 printk("PCIC: unimplemented code: FILE=%s LINE=%d", __FILE__, __LINE__); 849} 850 851void __init sun4m_pci_init_IRQ(void) 852{ 853 sparc_config.build_device_irq = pcic_build_device_irq; 854 sparc_config.clear_clock_irq = pcic_clear_clock_irq; 855 sparc_config.load_profile_irq = pcic_load_profile_irq; 856} 857 858subsys_initcall(pcic_init); 859