1/* 2 * SH7722 Setup 3 * 4 * Copyright (C) 2006 - 2008 Paul Mundt 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10#include <linux/init.h> 11#include <linux/mm.h> 12#include <linux/platform_device.h> 13#include <linux/serial.h> 14#include <linux/serial_sci.h> 15#include <linux/sh_dma.h> 16#include <linux/sh_timer.h> 17#include <linux/sh_intc.h> 18#include <linux/uio_driver.h> 19#include <linux/usb/m66592.h> 20 21#include <asm/clock.h> 22#include <asm/mmzone.h> 23#include <asm/siu.h> 24 25#include <cpu/dma-register.h> 26#include <cpu/sh7722.h> 27#include <cpu/serial.h> 28 29static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = { 30 { 31 .slave_id = SHDMA_SLAVE_SCIF0_TX, 32 .addr = 0xffe0000c, 33 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 34 .mid_rid = 0x21, 35 }, { 36 .slave_id = SHDMA_SLAVE_SCIF0_RX, 37 .addr = 0xffe00014, 38 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 39 .mid_rid = 0x22, 40 }, { 41 .slave_id = SHDMA_SLAVE_SCIF1_TX, 42 .addr = 0xffe1000c, 43 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 44 .mid_rid = 0x25, 45 }, { 46 .slave_id = SHDMA_SLAVE_SCIF1_RX, 47 .addr = 0xffe10014, 48 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 49 .mid_rid = 0x26, 50 }, { 51 .slave_id = SHDMA_SLAVE_SCIF2_TX, 52 .addr = 0xffe2000c, 53 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 54 .mid_rid = 0x29, 55 }, { 56 .slave_id = SHDMA_SLAVE_SCIF2_RX, 57 .addr = 0xffe20014, 58 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_8BIT), 59 .mid_rid = 0x2a, 60 }, { 61 .slave_id = SHDMA_SLAVE_SIUA_TX, 62 .addr = 0xa454c098, 63 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 64 .mid_rid = 0xb1, 65 }, { 66 .slave_id = SHDMA_SLAVE_SIUA_RX, 67 .addr = 0xa454c090, 68 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 69 .mid_rid = 0xb2, 70 }, { 71 .slave_id = SHDMA_SLAVE_SIUB_TX, 72 .addr = 0xa454c09c, 73 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 74 .mid_rid = 0xb5, 75 }, { 76 .slave_id = SHDMA_SLAVE_SIUB_RX, 77 .addr = 0xa454c094, 78 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_32BIT), 79 .mid_rid = 0xb6, 80 }, { 81 .slave_id = SHDMA_SLAVE_SDHI0_TX, 82 .addr = 0x04ce0030, 83 .chcr = DM_FIX | SM_INC | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), 84 .mid_rid = 0xc1, 85 }, { 86 .slave_id = SHDMA_SLAVE_SDHI0_RX, 87 .addr = 0x04ce0030, 88 .chcr = DM_INC | SM_FIX | RS_ERS | TS_INDEX2VAL(XMIT_SZ_16BIT), 89 .mid_rid = 0xc2, 90 }, 91}; 92 93static const struct sh_dmae_channel sh7722_dmae_channels[] = { 94 { 95 .offset = 0, 96 .dmars = 0, 97 .dmars_bit = 0, 98 }, { 99 .offset = 0x10, 100 .dmars = 0, 101 .dmars_bit = 8, 102 }, { 103 .offset = 0x20, 104 .dmars = 4, 105 .dmars_bit = 0, 106 }, { 107 .offset = 0x30, 108 .dmars = 4, 109 .dmars_bit = 8, 110 }, { 111 .offset = 0x50, 112 .dmars = 8, 113 .dmars_bit = 0, 114 }, { 115 .offset = 0x60, 116 .dmars = 8, 117 .dmars_bit = 8, 118 } 119}; 120 121static const unsigned int ts_shift[] = TS_SHIFT; 122 123static struct sh_dmae_pdata dma_platform_data = { 124 .slave = sh7722_dmae_slaves, 125 .slave_num = ARRAY_SIZE(sh7722_dmae_slaves), 126 .channel = sh7722_dmae_channels, 127 .channel_num = ARRAY_SIZE(sh7722_dmae_channels), 128 .ts_low_shift = CHCR_TS_LOW_SHIFT, 129 .ts_low_mask = CHCR_TS_LOW_MASK, 130 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 131 .ts_high_mask = CHCR_TS_HIGH_MASK, 132 .ts_shift = ts_shift, 133 .ts_shift_num = ARRAY_SIZE(ts_shift), 134 .dmaor_init = DMAOR_INIT, 135}; 136 137static struct resource sh7722_dmae_resources[] = { 138 [0] = { 139 /* Channel registers and DMAOR */ 140 .start = 0xfe008020, 141 .end = 0xfe00808f, 142 .flags = IORESOURCE_MEM, 143 }, 144 [1] = { 145 /* DMARSx */ 146 .start = 0xfe009000, 147 .end = 0xfe00900b, 148 .flags = IORESOURCE_MEM, 149 }, 150 { 151 .name = "error_irq", 152 .start = evt2irq(0xbc0), 153 .end = evt2irq(0xbc0), 154 .flags = IORESOURCE_IRQ, 155 }, 156 { 157 /* IRQ for channels 0-3 */ 158 .start = evt2irq(0x800), 159 .end = evt2irq(0x860), 160 .flags = IORESOURCE_IRQ, 161 }, 162 { 163 /* IRQ for channels 4-5 */ 164 .start = evt2irq(0xb80), 165 .end = evt2irq(0xba0), 166 .flags = IORESOURCE_IRQ, 167 }, 168}; 169 170struct platform_device dma_device = { 171 .name = "sh-dma-engine", 172 .id = -1, 173 .resource = sh7722_dmae_resources, 174 .num_resources = ARRAY_SIZE(sh7722_dmae_resources), 175 .dev = { 176 .platform_data = &dma_platform_data, 177 }, 178}; 179 180/* Serial */ 181static struct plat_sci_port scif0_platform_data = { 182 .flags = UPF_BOOT_AUTOCONF, 183 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 184 .type = PORT_SCIF, 185 .ops = &sh7722_sci_port_ops, 186 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 187}; 188 189static struct resource scif0_resources[] = { 190 DEFINE_RES_MEM(0xffe00000, 0x100), 191 DEFINE_RES_IRQ(evt2irq(0xc00)), 192}; 193 194static struct platform_device scif0_device = { 195 .name = "sh-sci", 196 .id = 0, 197 .resource = scif0_resources, 198 .num_resources = ARRAY_SIZE(scif0_resources), 199 .dev = { 200 .platform_data = &scif0_platform_data, 201 }, 202}; 203 204static struct plat_sci_port scif1_platform_data = { 205 .flags = UPF_BOOT_AUTOCONF, 206 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 207 .type = PORT_SCIF, 208 .ops = &sh7722_sci_port_ops, 209 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 210}; 211 212static struct resource scif1_resources[] = { 213 DEFINE_RES_MEM(0xffe10000, 0x100), 214 DEFINE_RES_IRQ(evt2irq(0xc20)), 215}; 216 217static struct platform_device scif1_device = { 218 .name = "sh-sci", 219 .id = 1, 220 .resource = scif1_resources, 221 .num_resources = ARRAY_SIZE(scif1_resources), 222 .dev = { 223 .platform_data = &scif1_platform_data, 224 }, 225}; 226 227static struct plat_sci_port scif2_platform_data = { 228 .flags = UPF_BOOT_AUTOCONF, 229 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 230 .type = PORT_SCIF, 231 .ops = &sh7722_sci_port_ops, 232 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 233}; 234 235static struct resource scif2_resources[] = { 236 DEFINE_RES_MEM(0xffe20000, 0x100), 237 DEFINE_RES_IRQ(evt2irq(0xc40)), 238}; 239 240static struct platform_device scif2_device = { 241 .name = "sh-sci", 242 .id = 2, 243 .resource = scif2_resources, 244 .num_resources = ARRAY_SIZE(scif2_resources), 245 .dev = { 246 .platform_data = &scif2_platform_data, 247 }, 248}; 249 250static struct resource rtc_resources[] = { 251 [0] = { 252 .start = 0xa465fec0, 253 .end = 0xa465fec0 + 0x58 - 1, 254 .flags = IORESOURCE_IO, 255 }, 256 [1] = { 257 /* Period IRQ */ 258 .start = evt2irq(0x7a0), 259 .flags = IORESOURCE_IRQ, 260 }, 261 [2] = { 262 /* Carry IRQ */ 263 .start = evt2irq(0x7c0), 264 .flags = IORESOURCE_IRQ, 265 }, 266 [3] = { 267 /* Alarm IRQ */ 268 .start = evt2irq(0x780), 269 .flags = IORESOURCE_IRQ, 270 }, 271}; 272 273static struct platform_device rtc_device = { 274 .name = "sh-rtc", 275 .id = -1, 276 .num_resources = ARRAY_SIZE(rtc_resources), 277 .resource = rtc_resources, 278}; 279 280static struct m66592_platdata usbf_platdata = { 281 .on_chip = 1, 282}; 283 284static struct resource usbf_resources[] = { 285 [0] = { 286 .name = "USBF", 287 .start = 0x04480000, 288 .end = 0x044800FF, 289 .flags = IORESOURCE_MEM, 290 }, 291 [1] = { 292 .start = evt2irq(0xa20), 293 .end = evt2irq(0xa20), 294 .flags = IORESOURCE_IRQ, 295 }, 296}; 297 298static struct platform_device usbf_device = { 299 .name = "m66592_udc", 300 .id = 0, /* "usbf0" clock */ 301 .dev = { 302 .dma_mask = NULL, 303 .coherent_dma_mask = 0xffffffff, 304 .platform_data = &usbf_platdata, 305 }, 306 .num_resources = ARRAY_SIZE(usbf_resources), 307 .resource = usbf_resources, 308}; 309 310static struct resource iic_resources[] = { 311 [0] = { 312 .name = "IIC", 313 .start = 0x04470000, 314 .end = 0x04470017, 315 .flags = IORESOURCE_MEM, 316 }, 317 [1] = { 318 .start = evt2irq(0xe00), 319 .end = evt2irq(0xe60), 320 .flags = IORESOURCE_IRQ, 321 }, 322}; 323 324static struct platform_device iic_device = { 325 .name = "i2c-sh_mobile", 326 .id = 0, /* "i2c0" clock */ 327 .num_resources = ARRAY_SIZE(iic_resources), 328 .resource = iic_resources, 329}; 330 331static struct uio_info vpu_platform_data = { 332 .name = "VPU4", 333 .version = "0", 334 .irq = evt2irq(0x980), 335}; 336 337static struct resource vpu_resources[] = { 338 [0] = { 339 .name = "VPU", 340 .start = 0xfe900000, 341 .end = 0xfe9022eb, 342 .flags = IORESOURCE_MEM, 343 }, 344 [1] = { 345 /* place holder for contiguous memory */ 346 }, 347}; 348 349static struct platform_device vpu_device = { 350 .name = "uio_pdrv_genirq", 351 .id = 0, 352 .dev = { 353 .platform_data = &vpu_platform_data, 354 }, 355 .resource = vpu_resources, 356 .num_resources = ARRAY_SIZE(vpu_resources), 357}; 358 359static struct uio_info veu_platform_data = { 360 .name = "VEU", 361 .version = "0", 362 .irq = evt2irq(0x8c0), 363}; 364 365static struct resource veu_resources[] = { 366 [0] = { 367 .name = "VEU", 368 .start = 0xfe920000, 369 .end = 0xfe9200b7, 370 .flags = IORESOURCE_MEM, 371 }, 372 [1] = { 373 /* place holder for contiguous memory */ 374 }, 375}; 376 377static struct platform_device veu_device = { 378 .name = "uio_pdrv_genirq", 379 .id = 1, 380 .dev = { 381 .platform_data = &veu_platform_data, 382 }, 383 .resource = veu_resources, 384 .num_resources = ARRAY_SIZE(veu_resources), 385}; 386 387static struct uio_info jpu_platform_data = { 388 .name = "JPU", 389 .version = "0", 390 .irq = evt2irq(0x560), 391}; 392 393static struct resource jpu_resources[] = { 394 [0] = { 395 .name = "JPU", 396 .start = 0xfea00000, 397 .end = 0xfea102d3, 398 .flags = IORESOURCE_MEM, 399 }, 400 [1] = { 401 /* place holder for contiguous memory */ 402 }, 403}; 404 405static struct platform_device jpu_device = { 406 .name = "uio_pdrv_genirq", 407 .id = 2, 408 .dev = { 409 .platform_data = &jpu_platform_data, 410 }, 411 .resource = jpu_resources, 412 .num_resources = ARRAY_SIZE(jpu_resources), 413}; 414 415static struct sh_timer_config cmt_platform_data = { 416 .channels_mask = 0x20, 417}; 418 419static struct resource cmt_resources[] = { 420 DEFINE_RES_MEM(0x044a0000, 0x70), 421 DEFINE_RES_IRQ(evt2irq(0xf00)), 422}; 423 424static struct platform_device cmt_device = { 425 .name = "sh-cmt-32", 426 .id = 0, 427 .dev = { 428 .platform_data = &cmt_platform_data, 429 }, 430 .resource = cmt_resources, 431 .num_resources = ARRAY_SIZE(cmt_resources), 432}; 433 434static struct sh_timer_config tmu0_platform_data = { 435 .channels_mask = 7, 436}; 437 438static struct resource tmu0_resources[] = { 439 DEFINE_RES_MEM(0xffd80000, 0x2c), 440 DEFINE_RES_IRQ(evt2irq(0x400)), 441 DEFINE_RES_IRQ(evt2irq(0x420)), 442 DEFINE_RES_IRQ(evt2irq(0x440)), 443}; 444 445static struct platform_device tmu0_device = { 446 .name = "sh-tmu", 447 .id = 0, 448 .dev = { 449 .platform_data = &tmu0_platform_data, 450 }, 451 .resource = tmu0_resources, 452 .num_resources = ARRAY_SIZE(tmu0_resources), 453}; 454 455static struct siu_platform siu_platform_data = { 456 .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX, 457 .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX, 458 .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX, 459 .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX, 460}; 461 462static struct resource siu_resources[] = { 463 [0] = { 464 .start = 0xa4540000, 465 .end = 0xa454c10f, 466 .flags = IORESOURCE_MEM, 467 }, 468 [1] = { 469 .start = evt2irq(0xf80), 470 .flags = IORESOURCE_IRQ, 471 }, 472}; 473 474static struct platform_device siu_device = { 475 .name = "siu-pcm-audio", 476 .id = -1, 477 .dev = { 478 .platform_data = &siu_platform_data, 479 }, 480 .resource = siu_resources, 481 .num_resources = ARRAY_SIZE(siu_resources), 482}; 483 484static struct platform_device *sh7722_devices[] __initdata = { 485 &scif0_device, 486 &scif1_device, 487 &scif2_device, 488 &cmt_device, 489 &tmu0_device, 490 &rtc_device, 491 &usbf_device, 492 &iic_device, 493 &vpu_device, 494 &veu_device, 495 &jpu_device, 496 &siu_device, 497 &dma_device, 498}; 499 500static int __init sh7722_devices_setup(void) 501{ 502 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); 503 platform_resource_setup_memory(&veu_device, "veu", 2 << 20); 504 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 505 506 return platform_add_devices(sh7722_devices, 507 ARRAY_SIZE(sh7722_devices)); 508} 509arch_initcall(sh7722_devices_setup); 510 511static struct platform_device *sh7722_early_devices[] __initdata = { 512 &scif0_device, 513 &scif1_device, 514 &scif2_device, 515 &cmt_device, 516 &tmu0_device, 517}; 518 519void __init plat_early_device_setup(void) 520{ 521 early_platform_add_devices(sh7722_early_devices, 522 ARRAY_SIZE(sh7722_early_devices)); 523} 524 525enum { 526 UNUSED=0, 527 ENABLED, 528 DISABLED, 529 530 /* interrupt sources */ 531 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 532 HUDI, 533 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI, 534 RTC_ATI, RTC_PRI, RTC_CUI, 535 DMAC0, DMAC1, DMAC2, DMAC3, 536 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU, 537 VPU, TPU, 538 USB_USBI0, USB_USBI1, 539 DMAC4, DMAC5, DMAC_DADERR, 540 KEYSC, 541 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO, 542 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 543 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI, 544 CMT, TSIF, SIU, TWODG, 545 TMU0, TMU1, TMU2, 546 IRDA, JPU, LCDC, 547 548 /* interrupt groups */ 549 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI, 550}; 551 552static struct intc_vect vectors[] __initdata = { 553 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), 554 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), 555 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), 556 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0), 557 INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720), 558 INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760), 559 INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0), 560 INTC_VECT(RTC_CUI, 0x7c0), 561 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820), 562 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860), 563 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0), 564 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0), 565 INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0), 566 INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40), 567 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0), 568 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0), 569 INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20), 570 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80), 571 INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00), 572 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0), 573 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0), 574 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20), 575 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60), 576 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0), 577 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0), 578 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20), 579 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0), 580 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 581 INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480), 582 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580), 583}; 584 585static struct intc_group groups[] __initdata = { 586 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI), 587 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 588 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), 589 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU), 590 INTC_GROUP(USB, USB_USBI0, USB_USBI1), 591 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR), 592 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI, 593 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 594 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI), 595}; 596 597static struct intc_mask_reg mask_registers[] __initdata = { 598 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ 599 { } }, 600 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ 601 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } }, 602 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */ 603 { 0, 0, 0, VPU, } }, 604 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */ 605 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } }, 606 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */ 607 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } }, 608 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */ 609 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } }, 610 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */ 611 { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } }, 612 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */ 613 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI, 614 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } }, 615 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */ 616 { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } }, 617 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */ 618 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } }, 619 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */ 620 { } }, 621 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */ 622 { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } }, 623 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */ 624 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 625}; 626 627static struct intc_prio_reg prio_registers[] __initdata = { 628 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } }, 629 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } }, 630 { 0xa4080008, 0, 16, 4, /* IPRC */ { } }, 631 { 0xa408000c, 0, 16, 4, /* IPRD */ { } }, 632 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } }, 633 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } }, 634 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } }, 635 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } }, 636 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } }, 637 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } }, 638 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } }, 639 { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } }, 640 { 0xa4140010, 0, 32, 4, /* INTPRI00 */ 641 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 642}; 643 644static struct intc_sense_reg sense_registers[] __initdata = { 645 { 0xa414001c, 16, 2, /* ICR1 */ 646 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 647}; 648 649static struct intc_mask_reg ack_registers[] __initdata = { 650 { 0xa4140024, 0, 8, /* INTREQ00 */ 651 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 652}; 653 654static struct intc_desc intc_desc __initdata = { 655 .name = "sh7722", 656 .force_enable = ENABLED, 657 .force_disable = DISABLED, 658 .hw = INTC_HW_DESC(vectors, groups, mask_registers, 659 prio_registers, sense_registers, ack_registers), 660}; 661 662void __init plat_irq_setup(void) 663{ 664 register_intc_controller(&intc_desc); 665} 666 667void __init plat_mem_setup(void) 668{ 669 /* Register the URAM space as Node 1 */ 670 setup_bootmem_node(1, 0x055f0000, 0x05610000); 671} 672