1/*
2 * SH4-202 Setup
3 *
4 *  Copyright (C) 2006  Paul Mundt
5 *  Copyright (C) 2009  Magnus Damm
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License.  See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/platform_device.h>
12#include <linux/init.h>
13#include <linux/serial.h>
14#include <linux/serial_sci.h>
15#include <linux/sh_timer.h>
16#include <linux/sh_intc.h>
17#include <linux/io.h>
18
19static struct plat_sci_port scif0_platform_data = {
20	.flags		= UPF_BOOT_AUTOCONF,
21	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_REIE,
22	.type		= PORT_SCIF,
23};
24
25static struct resource scif0_resources[] = {
26	DEFINE_RES_MEM(0xffe80000, 0x100),
27	DEFINE_RES_IRQ(evt2irq(0x700)),
28	DEFINE_RES_IRQ(evt2irq(0x720)),
29	DEFINE_RES_IRQ(evt2irq(0x760)),
30	DEFINE_RES_IRQ(evt2irq(0x740)),
31};
32
33static struct platform_device scif0_device = {
34	.name		= "sh-sci",
35	.id		= 0,
36	.resource	= scif0_resources,
37	.num_resources	= ARRAY_SIZE(scif0_resources),
38	.dev		= {
39		.platform_data	= &scif0_platform_data,
40	},
41};
42
43static struct sh_timer_config tmu0_platform_data = {
44	.channels_mask = 7,
45};
46
47static struct resource tmu0_resources[] = {
48	DEFINE_RES_MEM(0xffd80000, 0x30),
49	DEFINE_RES_IRQ(evt2irq(0x400)),
50	DEFINE_RES_IRQ(evt2irq(0x420)),
51	DEFINE_RES_IRQ(evt2irq(0x440)),
52};
53
54static struct platform_device tmu0_device = {
55	.name		= "sh-tmu",
56	.id		= 0,
57	.dev = {
58		.platform_data	= &tmu0_platform_data,
59	},
60	.resource	= tmu0_resources,
61	.num_resources	= ARRAY_SIZE(tmu0_resources),
62};
63
64static struct platform_device *sh4202_devices[] __initdata = {
65	&scif0_device,
66	&tmu0_device,
67};
68
69static int __init sh4202_devices_setup(void)
70{
71	return platform_add_devices(sh4202_devices,
72				    ARRAY_SIZE(sh4202_devices));
73}
74arch_initcall(sh4202_devices_setup);
75
76static struct platform_device *sh4202_early_devices[] __initdata = {
77	&scif0_device,
78	&tmu0_device,
79};
80
81void __init plat_early_device_setup(void)
82{
83	early_platform_add_devices(sh4202_early_devices,
84				   ARRAY_SIZE(sh4202_early_devices));
85}
86
87enum {
88	UNUSED = 0,
89
90	/* interrupt sources */
91	IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
92	HUDI, TMU0, TMU1, TMU2, RTC, SCIF, WDT,
93};
94
95static struct intc_vect vectors[] __initdata = {
96	INTC_VECT(HUDI, 0x600),
97	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
98	INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
99	INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
100	INTC_VECT(RTC, 0x4c0),
101	INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
102	INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
103	INTC_VECT(WDT, 0x560),
104};
105
106static struct intc_prio_reg prio_registers[] __initdata = {
107	{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
108	{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, 0, 0, 0 } },
109	{ 0xffd0000c, 0, 16, 4, /* IPRC */ { 0, 0, SCIF, HUDI } },
110	{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
111};
112
113static DECLARE_INTC_DESC(intc_desc, "sh4-202", vectors, NULL,
114			 NULL, prio_registers, NULL);
115
116static struct intc_vect vectors_irlm[] __initdata = {
117	INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
118	INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
119};
120
121static DECLARE_INTC_DESC(intc_desc_irlm, "sh4-202_irlm", vectors_irlm, NULL,
122			 NULL, prio_registers, NULL);
123
124void __init plat_irq_setup(void)
125{
126	register_intc_controller(&intc_desc);
127}
128
129#define INTC_ICR	0xffd00000UL
130#define INTC_ICR_IRLM   (1<<7)
131
132void __init plat_irq_setup_pins(int mode)
133{
134	switch (mode) {
135	case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
136		__raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
137		register_intc_controller(&intc_desc_irlm);
138		break;
139	default:
140		BUG();
141	}
142}
143