1#ifndef __ASM_CPU_SH3_DAC_H
2#define __ASM_CPU_SH3_DAC_H
3
4/*
5 * Copyright (C) 2003  Andriy Skulysh
6 */
7
8
9#define DADR0	0xa40000a0
10#define DADR1	0xa40000a2
11#define DACR	0xa40000a4
12#define DACR_DAOE1	0x80
13#define DACR_DAOE0	0x40
14#define DACR_DAE	0x20
15
16
17static __inline__ void sh_dac_enable(int channel)
18{
19	unsigned char v;
20	v = __raw_readb(DACR);
21	if(channel) v |= DACR_DAOE1;
22	else v |= DACR_DAOE0;
23	__raw_writeb(v,DACR);
24}
25
26static __inline__ void sh_dac_disable(int channel)
27{
28	unsigned char v;
29	v = __raw_readb(DACR);
30	if(channel) v &= ~DACR_DAOE1;
31	else v &= ~DACR_DAOE0;
32	__raw_writeb(v,DACR);
33}
34
35static __inline__ void sh_dac_output(u8 value, int channel)
36{
37	if(channel) __raw_writeb(value,DADR1);
38	else __raw_writeb(value,DADR0);
39}
40
41#endif /* __ASM_CPU_SH3_DAC_H */
42