1#include <linux/kernel.h>
2#include <linux/stddef.h>
3#include <linux/sched.h>
4#include <linux/signal.h>
5#include <linux/irq.h>
6#include <linux/dma-mapping.h>
7#include <asm/prom.h>
8#include <asm/irq.h>
9#include <asm/io.h>
10#include <asm/8xx_immap.h>
11
12#include "mpc8xx_pic.h"
13
14
15#define PIC_VEC_SPURRIOUS      15
16
17extern int cpm_get_irq(struct pt_regs *regs);
18
19static struct irq_domain *mpc8xx_pic_host;
20static unsigned long mpc8xx_cached_irq_mask;
21static sysconf8xx_t __iomem *siu_reg;
22
23static inline unsigned long mpc8xx_irqd_to_bit(struct irq_data *d)
24{
25	return 0x80000000 >> irqd_to_hwirq(d);
26}
27
28static void mpc8xx_unmask_irq(struct irq_data *d)
29{
30	mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d);
31	out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
32}
33
34static void mpc8xx_mask_irq(struct irq_data *d)
35{
36	mpc8xx_cached_irq_mask &= ~mpc8xx_irqd_to_bit(d);
37	out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
38}
39
40static void mpc8xx_ack(struct irq_data *d)
41{
42	out_be32(&siu_reg->sc_sipend, mpc8xx_irqd_to_bit(d));
43}
44
45static void mpc8xx_end_irq(struct irq_data *d)
46{
47	mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d);
48	out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
49}
50
51static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
52{
53	/* only external IRQ senses are programmable */
54	if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !(irqd_to_hwirq(d) & 1)) {
55		unsigned int siel = in_be32(&siu_reg->sc_siel);
56		siel |= mpc8xx_irqd_to_bit(d);
57		out_be32(&siu_reg->sc_siel, siel);
58		__irq_set_handler_locked(d->irq, handle_edge_irq);
59	}
60	return 0;
61}
62
63static struct irq_chip mpc8xx_pic = {
64	.name = "MPC8XX SIU",
65	.irq_unmask = mpc8xx_unmask_irq,
66	.irq_mask = mpc8xx_mask_irq,
67	.irq_ack = mpc8xx_ack,
68	.irq_eoi = mpc8xx_end_irq,
69	.irq_set_type = mpc8xx_set_irq_type,
70};
71
72unsigned int mpc8xx_get_irq(void)
73{
74	int irq;
75
76	/* For MPC8xx, read the SIVEC register and shift the bits down
77	 * to get the irq number.
78	 */
79	irq = in_be32(&siu_reg->sc_sivec) >> 26;
80
81	if (irq == PIC_VEC_SPURRIOUS)
82		irq = NO_IRQ;
83
84        return irq_linear_revmap(mpc8xx_pic_host, irq);
85
86}
87
88static int mpc8xx_pic_host_map(struct irq_domain *h, unsigned int virq,
89			  irq_hw_number_t hw)
90{
91	pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw);
92
93	/* Set default irq handle */
94	irq_set_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq);
95	return 0;
96}
97
98
99static int mpc8xx_pic_host_xlate(struct irq_domain *h, struct device_node *ct,
100			    const u32 *intspec, unsigned int intsize,
101			    irq_hw_number_t *out_hwirq, unsigned int *out_flags)
102{
103	static unsigned char map_pic_senses[4] = {
104		IRQ_TYPE_EDGE_RISING,
105		IRQ_TYPE_LEVEL_LOW,
106		IRQ_TYPE_LEVEL_HIGH,
107		IRQ_TYPE_EDGE_FALLING,
108	};
109
110	if (intspec[0] > 0x1f)
111		return 0;
112
113	*out_hwirq = intspec[0];
114	if (intsize > 1 && intspec[1] < 4)
115		*out_flags = map_pic_senses[intspec[1]];
116	else
117		*out_flags = IRQ_TYPE_NONE;
118
119	return 0;
120}
121
122
123static struct irq_domain_ops mpc8xx_pic_host_ops = {
124	.map = mpc8xx_pic_host_map,
125	.xlate = mpc8xx_pic_host_xlate,
126};
127
128int mpc8xx_pic_init(void)
129{
130	struct resource res;
131	struct device_node *np;
132	int ret;
133
134	np = of_find_compatible_node(NULL, NULL, "fsl,pq1-pic");
135	if (np == NULL)
136		np = of_find_node_by_type(NULL, "mpc8xx-pic");
137	if (np == NULL) {
138		printk(KERN_ERR "Could not find fsl,pq1-pic node\n");
139		return -ENOMEM;
140	}
141
142	ret = of_address_to_resource(np, 0, &res);
143	if (ret)
144		goto out;
145
146	siu_reg = ioremap(res.start, resource_size(&res));
147	if (siu_reg == NULL) {
148		ret = -EINVAL;
149		goto out;
150	}
151
152	mpc8xx_pic_host = irq_domain_add_linear(np, 64, &mpc8xx_pic_host_ops, NULL);
153	if (mpc8xx_pic_host == NULL) {
154		printk(KERN_ERR "MPC8xx PIC: failed to allocate irq host!\n");
155		ret = -ENOMEM;
156		goto out;
157	}
158	return 0;
159
160out:
161	of_node_put(np);
162	return ret;
163}
164