1/*
2 * Support for indirect PCI bridges.
3 *
4 * Copyright (C) 1998 Gabriel Paubert.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/pci.h>
14#include <linux/delay.h>
15#include <linux/string.h>
16#include <linux/init.h>
17
18#include <asm/io.h>
19#include <asm/prom.h>
20#include <asm/pci-bridge.h>
21#include <asm/machdep.h>
22
23int __indirect_read_config(struct pci_controller *hose,
24			   unsigned char bus_number, unsigned int devfn,
25			   int offset, int len, u32 *val)
26{
27	volatile void __iomem *cfg_data;
28	u8 cfg_type = 0;
29	u32 bus_no, reg;
30
31	if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
32		if (bus_number != hose->first_busno)
33			return PCIBIOS_DEVICE_NOT_FOUND;
34		if (devfn != 0)
35			return PCIBIOS_DEVICE_NOT_FOUND;
36	}
37
38	if (ppc_md.pci_exclude_device)
39		if (ppc_md.pci_exclude_device(hose, bus_number, devfn))
40			return PCIBIOS_DEVICE_NOT_FOUND;
41
42	if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
43		if (bus_number != hose->first_busno)
44			cfg_type = 1;
45
46	bus_no = (bus_number == hose->first_busno) ?
47			hose->self_busno : bus_number;
48
49	if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)
50		reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
51	else
52		reg = offset & 0xfc;
53
54	if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
55		out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
56			 (devfn << 8) | reg | cfg_type));
57	else
58		out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
59			 (devfn << 8) | reg | cfg_type));
60
61	/*
62	 * Note: the caller has already checked that offset is
63	 * suitably aligned and that len is 1, 2 or 4.
64	 */
65	cfg_data = hose->cfg_data + (offset & 3);
66	switch (len) {
67	case 1:
68		*val = in_8(cfg_data);
69		break;
70	case 2:
71		*val = in_le16(cfg_data);
72		break;
73	default:
74		*val = in_le32(cfg_data);
75		break;
76	}
77	return PCIBIOS_SUCCESSFUL;
78}
79
80int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
81			 int offset, int len, u32 *val)
82{
83	struct pci_controller *hose = pci_bus_to_host(bus);
84
85	return __indirect_read_config(hose, bus->number, devfn, offset, len,
86				      val);
87}
88
89int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
90			  int offset, int len, u32 val)
91{
92	struct pci_controller *hose = pci_bus_to_host(bus);
93	volatile void __iomem *cfg_data;
94	u8 cfg_type = 0;
95	u32 bus_no, reg;
96
97	if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
98		if (bus->number != hose->first_busno)
99			return PCIBIOS_DEVICE_NOT_FOUND;
100		if (devfn != 0)
101			return PCIBIOS_DEVICE_NOT_FOUND;
102	}
103
104	if (ppc_md.pci_exclude_device)
105		if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
106			return PCIBIOS_DEVICE_NOT_FOUND;
107
108	if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
109		if (bus->number != hose->first_busno)
110			cfg_type = 1;
111
112	bus_no = (bus->number == hose->first_busno) ?
113			hose->self_busno : bus->number;
114
115	if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)
116		reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
117	else
118		reg = offset & 0xfc;
119
120	if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
121		out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
122			 (devfn << 8) | reg | cfg_type));
123	else
124		out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
125			 (devfn << 8) | reg | cfg_type));
126
127	/* suppress setting of PCI_PRIMARY_BUS */
128	if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
129		if ((offset == PCI_PRIMARY_BUS) &&
130			(bus->number == hose->first_busno))
131		val &= 0xffffff00;
132
133	/* Workaround for PCI_28 Errata in 440EPx/GRx */
134	if ((hose->indirect_type & PPC_INDIRECT_TYPE_BROKEN_MRM) &&
135			offset == PCI_CACHE_LINE_SIZE) {
136		val = 0;
137	}
138
139	/*
140	 * Note: the caller has already checked that offset is
141	 * suitably aligned and that len is 1, 2 or 4.
142	 */
143	cfg_data = hose->cfg_data + (offset & 3);
144	switch (len) {
145	case 1:
146		out_8(cfg_data, val);
147		break;
148	case 2:
149		out_le16(cfg_data, val);
150		break;
151	default:
152		out_le32(cfg_data, val);
153		break;
154	}
155	return PCIBIOS_SUCCESSFUL;
156}
157
158static struct pci_ops indirect_pci_ops =
159{
160	.read = indirect_read_config,
161	.write = indirect_write_config,
162};
163
164void setup_indirect_pci(struct pci_controller *hose, resource_size_t cfg_addr,
165			resource_size_t cfg_data, u32 flags)
166{
167	resource_size_t base = cfg_addr & PAGE_MASK;
168	void __iomem *mbase;
169
170	mbase = ioremap(base, PAGE_SIZE);
171	hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);
172	if ((cfg_data & PAGE_MASK) != base)
173		mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
174	hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);
175	hose->ops = &indirect_pci_ops;
176	hose->indirect_type = flags;
177}
178