1/*
2 * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
3 *
4 * Author: Tony Li <tony.li@freescale.com>
5 *	   Jason Jin <Jason.jin@freescale.com>
6 *
7 * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; version 2 of the
12 * License.
13 *
14 */
15#include <linux/irq.h>
16#include <linux/msi.h>
17#include <linux/pci.h>
18#include <linux/slab.h>
19#include <linux/of_platform.h>
20#include <linux/interrupt.h>
21#include <linux/seq_file.h>
22#include <sysdev/fsl_soc.h>
23#include <asm/prom.h>
24#include <asm/hw_irq.h>
25#include <asm/ppc-pci.h>
26#include <asm/mpic.h>
27#include <asm/fsl_hcalls.h>
28
29#include "fsl_msi.h"
30#include "fsl_pci.h"
31
32#define MSIIR_OFFSET_MASK	0xfffff
33#define MSIIR_IBS_SHIFT		0
34#define MSIIR_SRS_SHIFT		5
35#define MSIIR1_IBS_SHIFT	4
36#define MSIIR1_SRS_SHIFT	0
37#define MSI_SRS_MASK		0xf
38#define MSI_IBS_MASK		0x1f
39
40#define msi_hwirq(msi, msir_index, intr_index) \
41		((msir_index) << (msi)->srs_shift | \
42		 ((intr_index) << (msi)->ibs_shift))
43
44static LIST_HEAD(msi_head);
45
46struct fsl_msi_feature {
47	u32 fsl_pic_ip;
48	u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */
49};
50
51struct fsl_msi_cascade_data {
52	struct fsl_msi *msi_data;
53	int index;
54	int virq;
55};
56
57static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
58{
59	return in_be32(base + (reg >> 2));
60}
61
62/*
63 * We do not need this actually. The MSIR register has been read once
64 * in the cascade interrupt. So, this MSI interrupt has been acked
65*/
66static void fsl_msi_end_irq(struct irq_data *d)
67{
68}
69
70static void fsl_msi_print_chip(struct irq_data *irqd, struct seq_file *p)
71{
72	struct fsl_msi *msi_data = irqd->domain->host_data;
73	irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
74	int cascade_virq, srs;
75
76	srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK;
77	cascade_virq = msi_data->cascade_array[srs]->virq;
78
79	seq_printf(p, " fsl-msi-%d", cascade_virq);
80}
81
82
83static struct irq_chip fsl_msi_chip = {
84	.irq_mask	= pci_msi_mask_irq,
85	.irq_unmask	= pci_msi_unmask_irq,
86	.irq_ack	= fsl_msi_end_irq,
87	.irq_print_chip = fsl_msi_print_chip,
88};
89
90static int fsl_msi_host_map(struct irq_domain *h, unsigned int virq,
91				irq_hw_number_t hw)
92{
93	struct fsl_msi *msi_data = h->host_data;
94	struct irq_chip *chip = &fsl_msi_chip;
95
96	irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);
97
98	irq_set_chip_data(virq, msi_data);
99	irq_set_chip_and_handler(virq, chip, handle_edge_irq);
100
101	return 0;
102}
103
104static const struct irq_domain_ops fsl_msi_host_ops = {
105	.map = fsl_msi_host_map,
106};
107
108static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
109{
110	int rc, hwirq;
111
112	rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS_MAX,
113			      msi_data->irqhost->of_node);
114	if (rc)
115		return rc;
116
117	/*
118	 * Reserve all the hwirqs
119	 * The available hwirqs will be released in fsl_msi_setup_hwirq()
120	 */
121	for (hwirq = 0; hwirq < NR_MSI_IRQS_MAX; hwirq++)
122		msi_bitmap_reserve_hwirq(&msi_data->bitmap, hwirq);
123
124	return 0;
125}
126
127static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
128{
129	struct msi_desc *entry;
130	struct fsl_msi *msi_data;
131	irq_hw_number_t hwirq;
132
133	list_for_each_entry(entry, &pdev->msi_list, list) {
134		if (entry->irq == NO_IRQ)
135			continue;
136		hwirq = virq_to_hw(entry->irq);
137		msi_data = irq_get_chip_data(entry->irq);
138		irq_set_msi_desc(entry->irq, NULL);
139		irq_dispose_mapping(entry->irq);
140		msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
141	}
142
143	return;
144}
145
146static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
147				struct msi_msg *msg,
148				struct fsl_msi *fsl_msi_data)
149{
150	struct fsl_msi *msi_data = fsl_msi_data;
151	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
152	u64 address; /* Physical address of the MSIIR */
153	int len;
154	const __be64 *reg;
155
156	/* If the msi-address-64 property exists, then use it */
157	reg = of_get_property(hose->dn, "msi-address-64", &len);
158	if (reg && (len == sizeof(u64)))
159		address = be64_to_cpup(reg);
160	else
161		address = fsl_pci_immrbar_base(hose) + msi_data->msiir_offset;
162
163	msg->address_lo = lower_32_bits(address);
164	msg->address_hi = upper_32_bits(address);
165
166	/*
167	 * MPIC version 2.0 has erratum PIC1. It causes
168	 * that neither MSI nor MSI-X can work fine.
169	 * This is a workaround to allow MSI-X to function
170	 * properly. It only works for MSI-X, we prevent
171	 * MSI on buggy chips in fsl_setup_msi_irqs().
172	 */
173	if (msi_data->feature & MSI_HW_ERRATA_ENDIAN)
174		msg->data = __swab32(hwirq);
175	else
176		msg->data = hwirq;
177
178	pr_debug("%s: allocated srs: %d, ibs: %d\n", __func__,
179		 (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK,
180		 (hwirq >> msi_data->ibs_shift) & MSI_IBS_MASK);
181}
182
183static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
184{
185	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
186	struct device_node *np;
187	phandle phandle = 0;
188	int rc, hwirq = -ENOMEM;
189	unsigned int virq;
190	struct msi_desc *entry;
191	struct msi_msg msg;
192	struct fsl_msi *msi_data;
193
194	if (type == PCI_CAP_ID_MSI) {
195		/*
196		 * MPIC version 2.0 has erratum PIC1. For now MSI
197		 * could not work. So check to prevent MSI from
198		 * being used on the board with this erratum.
199		 */
200		list_for_each_entry(msi_data, &msi_head, list)
201			if (msi_data->feature & MSI_HW_ERRATA_ENDIAN)
202				return -EINVAL;
203	}
204
205	/*
206	 * If the PCI node has an fsl,msi property, then we need to use it
207	 * to find the specific MSI.
208	 */
209	np = of_parse_phandle(hose->dn, "fsl,msi", 0);
210	if (np) {
211		if (of_device_is_compatible(np, "fsl,mpic-msi") ||
212		    of_device_is_compatible(np, "fsl,vmpic-msi") ||
213		    of_device_is_compatible(np, "fsl,vmpic-msi-v4.3"))
214			phandle = np->phandle;
215		else {
216			dev_err(&pdev->dev,
217				"node %s has an invalid fsl,msi phandle %u\n",
218				hose->dn->full_name, np->phandle);
219			return -EINVAL;
220		}
221	}
222
223	list_for_each_entry(entry, &pdev->msi_list, list) {
224		/*
225		 * Loop over all the MSI devices until we find one that has an
226		 * available interrupt.
227		 */
228		list_for_each_entry(msi_data, &msi_head, list) {
229			/*
230			 * If the PCI node has an fsl,msi property, then we
231			 * restrict our search to the corresponding MSI node.
232			 * The simplest way is to skip over MSI nodes with the
233			 * wrong phandle. Under the Freescale hypervisor, this
234			 * has the additional benefit of skipping over MSI
235			 * nodes that are not mapped in the PAMU.
236			 */
237			if (phandle && (phandle != msi_data->phandle))
238				continue;
239
240			hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
241			if (hwirq >= 0)
242				break;
243		}
244
245		if (hwirq < 0) {
246			rc = hwirq;
247			dev_err(&pdev->dev, "could not allocate MSI interrupt\n");
248			goto out_free;
249		}
250
251		virq = irq_create_mapping(msi_data->irqhost, hwirq);
252
253		if (virq == NO_IRQ) {
254			dev_err(&pdev->dev, "fail mapping hwirq %i\n", hwirq);
255			msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
256			rc = -ENOSPC;
257			goto out_free;
258		}
259		/* chip_data is msi_data via host->hostdata in host->map() */
260		irq_set_msi_desc(virq, entry);
261
262		fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
263		pci_write_msi_msg(virq, &msg);
264	}
265	return 0;
266
267out_free:
268	/* free by the caller of this function */
269	return rc;
270}
271
272static irqreturn_t fsl_msi_cascade(int irq, void *data)
273{
274	unsigned int cascade_irq;
275	struct fsl_msi *msi_data;
276	int msir_index = -1;
277	u32 msir_value = 0;
278	u32 intr_index;
279	u32 have_shift = 0;
280	struct fsl_msi_cascade_data *cascade_data = data;
281	irqreturn_t ret = IRQ_NONE;
282
283	msi_data = cascade_data->msi_data;
284
285	msir_index = cascade_data->index;
286
287	if (msir_index >= NR_MSI_REG_MAX)
288		cascade_irq = NO_IRQ;
289
290	switch (msi_data->feature & FSL_PIC_IP_MASK) {
291	case FSL_PIC_IP_MPIC:
292		msir_value = fsl_msi_read(msi_data->msi_regs,
293			msir_index * 0x10);
294		break;
295	case FSL_PIC_IP_IPIC:
296		msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
297		break;
298#ifdef CONFIG_EPAPR_PARAVIRT
299	case FSL_PIC_IP_VMPIC: {
300		unsigned int ret;
301		ret = fh_vmpic_get_msir(virq_to_hw(irq), &msir_value);
302		if (ret) {
303			pr_err("fsl-msi: fh_vmpic_get_msir() failed for "
304			       "irq %u (ret=%u)\n", irq, ret);
305			msir_value = 0;
306		}
307		break;
308	}
309#endif
310	}
311
312	while (msir_value) {
313		intr_index = ffs(msir_value) - 1;
314
315		cascade_irq = irq_linear_revmap(msi_data->irqhost,
316				msi_hwirq(msi_data, msir_index,
317					  intr_index + have_shift));
318		if (cascade_irq != NO_IRQ) {
319			generic_handle_irq(cascade_irq);
320			ret = IRQ_HANDLED;
321		}
322		have_shift += intr_index + 1;
323		msir_value = msir_value >> (intr_index + 1);
324	}
325
326	return ret;
327}
328
329static int fsl_of_msi_remove(struct platform_device *ofdev)
330{
331	struct fsl_msi *msi = platform_get_drvdata(ofdev);
332	int virq, i;
333
334	if (msi->list.prev != NULL)
335		list_del(&msi->list);
336	for (i = 0; i < NR_MSI_REG_MAX; i++) {
337		if (msi->cascade_array[i]) {
338			virq = msi->cascade_array[i]->virq;
339
340			BUG_ON(virq == NO_IRQ);
341
342			free_irq(virq, msi->cascade_array[i]);
343			kfree(msi->cascade_array[i]);
344			irq_dispose_mapping(virq);
345		}
346	}
347	if (msi->bitmap.bitmap)
348		msi_bitmap_free(&msi->bitmap);
349	if ((msi->feature & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC)
350		iounmap(msi->msi_regs);
351	kfree(msi);
352
353	return 0;
354}
355
356static struct lock_class_key fsl_msi_irq_class;
357
358static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
359			       int offset, int irq_index)
360{
361	struct fsl_msi_cascade_data *cascade_data = NULL;
362	int virt_msir, i, ret;
363
364	virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
365	if (virt_msir == NO_IRQ) {
366		dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n",
367			__func__, irq_index);
368		return 0;
369	}
370
371	cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL);
372	if (!cascade_data) {
373		dev_err(&dev->dev, "No memory for MSI cascade data\n");
374		return -ENOMEM;
375	}
376	irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class);
377	cascade_data->index = offset;
378	cascade_data->msi_data = msi;
379	cascade_data->virq = virt_msir;
380	msi->cascade_array[irq_index] = cascade_data;
381
382	ret = request_irq(virt_msir, fsl_msi_cascade, IRQF_NO_THREAD,
383			  "fsl-msi-cascade", cascade_data);
384	if (ret) {
385		dev_err(&dev->dev, "failed to request_irq(%d), ret = %d\n",
386			virt_msir, ret);
387		return ret;
388	}
389
390	/* Release the hwirqs corresponding to this MSI register */
391	for (i = 0; i < IRQS_PER_MSI_REG; i++)
392		msi_bitmap_free_hwirqs(&msi->bitmap,
393				       msi_hwirq(msi, offset, i), 1);
394
395	return 0;
396}
397
398static const struct of_device_id fsl_of_msi_ids[];
399static int fsl_of_msi_probe(struct platform_device *dev)
400{
401	const struct of_device_id *match;
402	struct fsl_msi *msi;
403	struct resource res, msiir;
404	int err, i, j, irq_index, count;
405	const u32 *p;
406	const struct fsl_msi_feature *features;
407	int len;
408	u32 offset;
409
410	match = of_match_device(fsl_of_msi_ids, &dev->dev);
411	if (!match)
412		return -EINVAL;
413	features = match->data;
414
415	printk(KERN_DEBUG "Setting up Freescale MSI support\n");
416
417	msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
418	if (!msi) {
419		dev_err(&dev->dev, "No memory for MSI structure\n");
420		return -ENOMEM;
421	}
422	platform_set_drvdata(dev, msi);
423
424	msi->irqhost = irq_domain_add_linear(dev->dev.of_node,
425				      NR_MSI_IRQS_MAX, &fsl_msi_host_ops, msi);
426
427	if (msi->irqhost == NULL) {
428		dev_err(&dev->dev, "No memory for MSI irqhost\n");
429		err = -ENOMEM;
430		goto error_out;
431	}
432
433	/*
434	 * Under the Freescale hypervisor, the msi nodes don't have a 'reg'
435	 * property.  Instead, we use hypercalls to access the MSI.
436	 */
437	if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) {
438		err = of_address_to_resource(dev->dev.of_node, 0, &res);
439		if (err) {
440			dev_err(&dev->dev, "invalid resource for node %s\n",
441				dev->dev.of_node->full_name);
442			goto error_out;
443		}
444
445		msi->msi_regs = ioremap(res.start, resource_size(&res));
446		if (!msi->msi_regs) {
447			err = -ENOMEM;
448			dev_err(&dev->dev, "could not map node %s\n",
449				dev->dev.of_node->full_name);
450			goto error_out;
451		}
452		msi->msiir_offset =
453			features->msiir_offset + (res.start & 0xfffff);
454
455		/*
456		 * First read the MSIIR/MSIIR1 offset from dts
457		 * On failure use the hardcode MSIIR offset
458		 */
459		if (of_address_to_resource(dev->dev.of_node, 1, &msiir))
460			msi->msiir_offset = features->msiir_offset +
461					    (res.start & MSIIR_OFFSET_MASK);
462		else
463			msi->msiir_offset = msiir.start & MSIIR_OFFSET_MASK;
464	}
465
466	msi->feature = features->fsl_pic_ip;
467
468	/* For erratum PIC1 on MPIC version 2.0*/
469	if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) == FSL_PIC_IP_MPIC
470			&& (fsl_mpic_primary_get_version() == 0x0200))
471		msi->feature |= MSI_HW_ERRATA_ENDIAN;
472
473	/*
474	 * Remember the phandle, so that we can match with any PCI nodes
475	 * that have an "fsl,msi" property.
476	 */
477	msi->phandle = dev->dev.of_node->phandle;
478
479	err = fsl_msi_init_allocator(msi);
480	if (err) {
481		dev_err(&dev->dev, "Error allocating MSI bitmap\n");
482		goto error_out;
483	}
484
485	p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
486
487	if (of_device_is_compatible(dev->dev.of_node, "fsl,mpic-msi-v4.3") ||
488	    of_device_is_compatible(dev->dev.of_node, "fsl,vmpic-msi-v4.3")) {
489		msi->srs_shift = MSIIR1_SRS_SHIFT;
490		msi->ibs_shift = MSIIR1_IBS_SHIFT;
491		if (p)
492			dev_warn(&dev->dev, "%s: dose not support msi-available-ranges property\n",
493				__func__);
494
495		for (irq_index = 0; irq_index < NR_MSI_REG_MSIIR1;
496		     irq_index++) {
497			err = fsl_msi_setup_hwirq(msi, dev,
498						  irq_index, irq_index);
499			if (err)
500				goto error_out;
501		}
502	} else {
503		static const u32 all_avail[] =
504			{ 0, NR_MSI_REG_MSIIR * IRQS_PER_MSI_REG };
505
506		msi->srs_shift = MSIIR_SRS_SHIFT;
507		msi->ibs_shift = MSIIR_IBS_SHIFT;
508
509		if (p && len % (2 * sizeof(u32)) != 0) {
510			dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
511				__func__);
512			err = -EINVAL;
513			goto error_out;
514		}
515
516		if (!p) {
517			p = all_avail;
518			len = sizeof(all_avail);
519		}
520
521		for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
522			if (p[i * 2] % IRQS_PER_MSI_REG ||
523			    p[i * 2 + 1] % IRQS_PER_MSI_REG) {
524				pr_warn("%s: %s: msi available range of %u at %u is not IRQ-aligned\n",
525				       __func__, dev->dev.of_node->full_name,
526				       p[i * 2 + 1], p[i * 2]);
527				err = -EINVAL;
528				goto error_out;
529			}
530
531			offset = p[i * 2] / IRQS_PER_MSI_REG;
532			count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
533
534			for (j = 0; j < count; j++, irq_index++) {
535				err = fsl_msi_setup_hwirq(msi, dev, offset + j,
536							  irq_index);
537				if (err)
538					goto error_out;
539			}
540		}
541	}
542
543	list_add_tail(&msi->list, &msi_head);
544
545	/* The multiple setting ppc_md.setup_msi_irqs will not harm things */
546	if (!ppc_md.setup_msi_irqs) {
547		ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
548		ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
549	} else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
550		dev_err(&dev->dev, "Different MSI driver already installed!\n");
551		err = -ENODEV;
552		goto error_out;
553	}
554	return 0;
555error_out:
556	fsl_of_msi_remove(dev);
557	return err;
558}
559
560static const struct fsl_msi_feature mpic_msi_feature = {
561	.fsl_pic_ip = FSL_PIC_IP_MPIC,
562	.msiir_offset = 0x140,
563};
564
565static const struct fsl_msi_feature ipic_msi_feature = {
566	.fsl_pic_ip = FSL_PIC_IP_IPIC,
567	.msiir_offset = 0x38,
568};
569
570static const struct fsl_msi_feature vmpic_msi_feature = {
571	.fsl_pic_ip = FSL_PIC_IP_VMPIC,
572	.msiir_offset = 0,
573};
574
575static const struct of_device_id fsl_of_msi_ids[] = {
576	{
577		.compatible = "fsl,mpic-msi",
578		.data = &mpic_msi_feature,
579	},
580	{
581		.compatible = "fsl,mpic-msi-v4.3",
582		.data = &mpic_msi_feature,
583	},
584	{
585		.compatible = "fsl,ipic-msi",
586		.data = &ipic_msi_feature,
587	},
588#ifdef CONFIG_EPAPR_PARAVIRT
589	{
590		.compatible = "fsl,vmpic-msi",
591		.data = &vmpic_msi_feature,
592	},
593	{
594		.compatible = "fsl,vmpic-msi-v4.3",
595		.data = &vmpic_msi_feature,
596	},
597#endif
598	{}
599};
600
601static struct platform_driver fsl_of_msi_driver = {
602	.driver = {
603		.name = "fsl-msi",
604		.of_match_table = fsl_of_msi_ids,
605	},
606	.probe = fsl_of_msi_probe,
607	.remove = fsl_of_msi_remove,
608};
609
610static __init int fsl_of_msi_init(void)
611{
612	return platform_driver_register(&fsl_of_msi_driver);
613}
614
615subsys_initcall(fsl_of_msi_init);
616