1#ifndef __POWERNV_PCI_H
2#define __POWERNV_PCI_H
3
4struct pci_dn;
5
6enum pnv_phb_type {
7	PNV_PHB_P5IOC2	= 0,
8	PNV_PHB_IODA1	= 1,
9	PNV_PHB_IODA2	= 2,
10};
11
12/* Precise PHB model for error management */
13enum pnv_phb_model {
14	PNV_PHB_MODEL_UNKNOWN,
15	PNV_PHB_MODEL_P5IOC2,
16	PNV_PHB_MODEL_P7IOC,
17	PNV_PHB_MODEL_PHB3,
18};
19
20#define PNV_PCI_DIAG_BUF_SIZE	8192
21#define PNV_IODA_PE_DEV		(1 << 0)	/* PE has single PCI device	*/
22#define PNV_IODA_PE_BUS		(1 << 1)	/* PE has primary PCI bus	*/
23#define PNV_IODA_PE_BUS_ALL	(1 << 2)	/* PE has subordinate buses	*/
24#define PNV_IODA_PE_MASTER	(1 << 3)	/* Master PE in compound case	*/
25#define PNV_IODA_PE_SLAVE	(1 << 4)	/* Slave PE in compound case	*/
26#define PNV_IODA_PE_VF		(1 << 5)	/* PE for one VF 		*/
27
28/* Data associated with a PE, including IOMMU tracking etc.. */
29struct pnv_phb;
30struct pnv_ioda_pe {
31	unsigned long		flags;
32	struct pnv_phb		*phb;
33
34	/* A PE can be associated with a single device or an
35	 * entire bus (& children). In the former case, pdev
36	 * is populated, in the later case, pbus is.
37	 */
38#ifdef CONFIG_PCI_IOV
39	struct pci_dev          *parent_dev;
40#endif
41	struct pci_dev		*pdev;
42	struct pci_bus		*pbus;
43
44	/* Effective RID (device RID for a device PE and base bus
45	 * RID with devfn 0 for a bus PE)
46	 */
47	unsigned int		rid;
48
49	/* PE number */
50	unsigned int		pe_number;
51
52	/* "Weight" assigned to the PE for the sake of DMA resource
53	 * allocations
54	 */
55	unsigned int		dma_weight;
56
57	/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
58	int			tce32_seg;
59	int			tce32_segcount;
60	struct iommu_table	*tce32_table;
61	phys_addr_t		tce_inval_reg_phys;
62
63	/* 64-bit TCE bypass region */
64	bool			tce_bypass_enabled;
65	uint64_t		tce_bypass_base;
66
67	/* MSIs. MVE index is identical for for 32 and 64 bit MSI
68	 * and -1 if not supported. (It's actually identical to the
69	 * PE number)
70	 */
71	int			mve_number;
72
73	/* PEs in compound case */
74	struct pnv_ioda_pe	*master;
75	struct list_head	slaves;
76
77	/* Link in list of PE#s */
78	struct list_head	dma_link;
79	struct list_head	list;
80};
81
82#define PNV_PHB_FLAG_EEH	(1 << 0)
83
84struct pnv_phb {
85	struct pci_controller	*hose;
86	enum pnv_phb_type	type;
87	enum pnv_phb_model	model;
88	u64			hub_id;
89	u64			opal_id;
90	int			flags;
91	void __iomem		*regs;
92	int			initialized;
93	spinlock_t		lock;
94
95#ifdef CONFIG_DEBUG_FS
96	int			has_dbgfs;
97	struct dentry		*dbgfs;
98#endif
99
100#ifdef CONFIG_PCI_MSI
101	unsigned int		msi_base;
102	unsigned int		msi32_support;
103	struct msi_bitmap	msi_bmp;
104#endif
105	int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
106			 unsigned int hwirq, unsigned int virq,
107			 unsigned int is_64, struct msi_msg *msg);
108	void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
109	int (*dma_set_mask)(struct pnv_phb *phb, struct pci_dev *pdev,
110			    u64 dma_mask);
111	u64 (*dma_get_required_mask)(struct pnv_phb *phb,
112				     struct pci_dev *pdev);
113	void (*fixup_phb)(struct pci_controller *hose);
114	u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
115	void (*shutdown)(struct pnv_phb *phb);
116	int (*init_m64)(struct pnv_phb *phb);
117	void (*reserve_m64_pe)(struct pnv_phb *phb);
118	int (*pick_m64_pe)(struct pnv_phb *phb, struct pci_bus *bus, int all);
119	int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
120	void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
121	int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
122
123	union {
124		struct {
125			struct iommu_table iommu_table;
126		} p5ioc2;
127
128		struct {
129			/* Global bridge info */
130			unsigned int		total_pe;
131			unsigned int		reserved_pe;
132
133			/* 32-bit MMIO window */
134			unsigned int		m32_size;
135			unsigned int		m32_segsize;
136			unsigned int		m32_pci_base;
137
138			/* 64-bit MMIO window */
139			unsigned int		m64_bar_idx;
140			unsigned long		m64_size;
141			unsigned long		m64_segsize;
142			unsigned long		m64_base;
143			unsigned long		m64_bar_alloc;
144
145			/* IO ports */
146			unsigned int		io_size;
147			unsigned int		io_segsize;
148			unsigned int		io_pci_base;
149
150			/* PE allocation bitmap */
151			unsigned long		*pe_alloc;
152			/* PE allocation mutex */
153			struct mutex		pe_alloc_mutex;
154
155			/* M32 & IO segment maps */
156			unsigned int		*m32_segmap;
157			unsigned int		*io_segmap;
158			struct pnv_ioda_pe	*pe_array;
159
160			/* IRQ chip */
161			int			irq_chip_init;
162			struct irq_chip		irq_chip;
163
164			/* Sorted list of used PE's based
165			 * on the sequence of creation
166			 */
167			struct list_head	pe_list;
168			struct mutex            pe_list_mutex;
169
170			/* Reverse map of PEs, will have to extend if
171			 * we are to support more than 256 PEs, indexed
172			 * bus { bus, devfn }
173			 */
174			unsigned char		pe_rmap[0x10000];
175
176			/* 32-bit TCE tables allocation */
177			unsigned long		tce32_count;
178
179			/* Total "weight" for the sake of DMA resources
180			 * allocation
181			 */
182			unsigned int		dma_weight;
183			unsigned int		dma_pe_count;
184
185			/* Sorted list of used PE's, sorted at
186			 * boot for resource allocation purposes
187			 */
188			struct list_head	pe_dma_list;
189		} ioda;
190	};
191
192	/* PHB and hub status structure */
193	union {
194		unsigned char			blob[PNV_PCI_DIAG_BUF_SIZE];
195		struct OpalIoP7IOCPhbErrorData	p7ioc;
196		struct OpalIoPhb3ErrorData	phb3;
197		struct OpalIoP7IOCErrorData 	hub_diag;
198	} diag;
199
200};
201
202extern struct pci_ops pnv_pci_ops;
203
204void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
205				unsigned char *log_buff);
206int pnv_pci_cfg_read(struct pci_dn *pdn,
207		     int where, int size, u32 *val);
208int pnv_pci_cfg_write(struct pci_dn *pdn,
209		      int where, int size, u32 val);
210extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
211				      void *tce_mem, u64 tce_size,
212				      u64 dma_offset, unsigned page_shift);
213extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
214extern void pnv_pci_init_ioda_hub(struct device_node *np);
215extern void pnv_pci_init_ioda2_phb(struct device_node *np);
216extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
217					__be64 *startp, __be64 *endp, bool rm);
218extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
219extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
220
221#endif /* __POWERNV_PCI_H */
222