1/* 2 * MPC8610 HPCD board specific routines 3 * 4 * Initial author: Xianghua Xiao <x.xiao@freescale.com> 5 * Recode: Jason Jin <jason.jin@freescale.com> 6 * York Sun <yorksun@freescale.com> 7 * 8 * Rewrite the interrupt routing. remove the 8259PIC support, 9 * All the integrated device in ULI use sideband interrupt. 10 * 11 * Copyright 2008 Freescale Semiconductor Inc. 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 */ 18 19#include <linux/stddef.h> 20#include <linux/kernel.h> 21#include <linux/pci.h> 22#include <linux/interrupt.h> 23#include <linux/kdev_t.h> 24#include <linux/delay.h> 25#include <linux/seq_file.h> 26#include <linux/of.h> 27 28#include <asm/time.h> 29#include <asm/machdep.h> 30#include <asm/pci-bridge.h> 31#include <asm/prom.h> 32#include <mm/mmu_decl.h> 33#include <asm/udbg.h> 34 35#include <asm/mpic.h> 36 37#include <linux/of_platform.h> 38#include <sysdev/fsl_pci.h> 39#include <sysdev/fsl_soc.h> 40#include <sysdev/simple_gpio.h> 41#include <asm/fsl_guts.h> 42 43#include "mpc86xx.h" 44 45static struct device_node *pixis_node; 46static unsigned char *pixis_bdcfg0, *pixis_arch; 47 48/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */ 49#define CLKDVDR_PXCKEN 0x80000000 50#define CLKDVDR_PXCKINV 0x10000000 51#define CLKDVDR_PXCKDLY 0x06000000 52#define CLKDVDR_PXCLK_MASK 0x001F0000 53 54#ifdef CONFIG_SUSPEND 55static irqreturn_t mpc8610_sw9_irq(int irq, void *data) 56{ 57 pr_debug("%s: PIXIS' event (sw9/wakeup) IRQ handled\n", __func__); 58 return IRQ_HANDLED; 59} 60 61static void __init mpc8610_suspend_init(void) 62{ 63 int irq; 64 int ret; 65 66 if (!pixis_node) 67 return; 68 69 irq = irq_of_parse_and_map(pixis_node, 0); 70 if (!irq) { 71 pr_err("%s: can't map pixis event IRQ.\n", __func__); 72 return; 73 } 74 75 ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9:wakeup", NULL); 76 if (ret) { 77 pr_err("%s: can't request pixis event IRQ: %d\n", 78 __func__, ret); 79 irq_dispose_mapping(irq); 80 } 81 82 enable_irq_wake(irq); 83} 84#else 85static inline void mpc8610_suspend_init(void) { } 86#endif /* CONFIG_SUSPEND */ 87 88static const struct of_device_id mpc8610_ids[] __initconst = { 89 { .compatible = "fsl,mpc8610-immr", }, 90 { .compatible = "fsl,mpc8610-guts", }, 91 { .compatible = "simple-bus", }, 92 /* So that the DMA channel nodes can be probed individually: */ 93 { .compatible = "fsl,eloplus-dma", }, 94 /* PCI controllers */ 95 { .compatible = "fsl,mpc8610-pci", }, 96 { .compatible = "fsl,mpc8641-pcie", }, 97 {} 98}; 99 100static int __init mpc8610_declare_of_platform_devices(void) 101{ 102 /* Firstly, register PIXIS GPIOs. */ 103 simple_gpiochip_init("fsl,fpga-pixis-gpio-bank"); 104 105 /* Enable wakeup on PIXIS' event IRQ. */ 106 mpc8610_suspend_init(); 107 108 /* Without this call, the SSI device driver won't get probed. */ 109 of_platform_bus_probe(NULL, mpc8610_ids, NULL); 110 111 return 0; 112} 113machine_arch_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices); 114 115#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) 116 117/* 118 * DIU Area Descriptor 119 * 120 * The MPC8610 reference manual shows the bits of the AD register in 121 * little-endian order, which causes the BLUE_C field to be split into two 122 * parts. To simplify the definition of the MAKE_AD() macro, we define the 123 * fields in big-endian order and byte-swap the result. 124 * 125 * So even though the registers don't look like they're in the 126 * same bit positions as they are on the P1022, the same value is written to 127 * the AD register on the MPC8610 and on the P1022. 128 */ 129#define AD_BYTE_F 0x10000000 130#define AD_ALPHA_C_MASK 0x0E000000 131#define AD_ALPHA_C_SHIFT 25 132#define AD_BLUE_C_MASK 0x01800000 133#define AD_BLUE_C_SHIFT 23 134#define AD_GREEN_C_MASK 0x00600000 135#define AD_GREEN_C_SHIFT 21 136#define AD_RED_C_MASK 0x00180000 137#define AD_RED_C_SHIFT 19 138#define AD_PALETTE 0x00040000 139#define AD_PIXEL_S_MASK 0x00030000 140#define AD_PIXEL_S_SHIFT 16 141#define AD_COMP_3_MASK 0x0000F000 142#define AD_COMP_3_SHIFT 12 143#define AD_COMP_2_MASK 0x00000F00 144#define AD_COMP_2_SHIFT 8 145#define AD_COMP_1_MASK 0x000000F0 146#define AD_COMP_1_SHIFT 4 147#define AD_COMP_0_MASK 0x0000000F 148#define AD_COMP_0_SHIFT 0 149 150#define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \ 151 cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \ 152 (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \ 153 (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \ 154 (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \ 155 (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT)) 156 157u32 mpc8610hpcd_get_pixel_format(enum fsl_diu_monitor_port port, 158 unsigned int bits_per_pixel) 159{ 160 static const u32 pixelformat[][3] = { 161 { 162 MAKE_AD(3, 0, 2, 1, 3, 8, 8, 8, 8), 163 MAKE_AD(4, 2, 0, 1, 2, 8, 8, 8, 0), 164 MAKE_AD(4, 0, 2, 1, 1, 5, 6, 5, 0) 165 }, 166 { 167 MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8), 168 MAKE_AD(4, 0, 2, 1, 2, 8, 8, 8, 0), 169 MAKE_AD(4, 2, 0, 1, 1, 5, 6, 5, 0) 170 }, 171 }; 172 unsigned int arch_monitor; 173 174 /* The DVI port is mis-wired on revision 1 of this board. */ 175 arch_monitor = 176 ((*pixis_arch == 0x01) && (port == FSL_DIU_PORT_DVI)) ? 0 : 1; 177 178 switch (bits_per_pixel) { 179 case 32: 180 return pixelformat[arch_monitor][0]; 181 case 24: 182 return pixelformat[arch_monitor][1]; 183 case 16: 184 return pixelformat[arch_monitor][2]; 185 default: 186 pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel); 187 return 0; 188 } 189} 190 191void mpc8610hpcd_set_gamma_table(enum fsl_diu_monitor_port port, 192 char *gamma_table_base) 193{ 194 int i; 195 if (port == FSL_DIU_PORT_DLVDS) { 196 for (i = 0; i < 256*3; i++) 197 gamma_table_base[i] = (gamma_table_base[i] << 2) | 198 ((gamma_table_base[i] >> 6) & 0x03); 199 } 200} 201 202#define PX_BRDCFG0_DVISEL (1 << 3) 203#define PX_BRDCFG0_DLINK (1 << 4) 204#define PX_BRDCFG0_DIU_MASK (PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK) 205 206void mpc8610hpcd_set_monitor_port(enum fsl_diu_monitor_port port) 207{ 208 switch (port) { 209 case FSL_DIU_PORT_DVI: 210 clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK, 211 PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK); 212 break; 213 case FSL_DIU_PORT_LVDS: 214 clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK, 215 PX_BRDCFG0_DLINK); 216 break; 217 case FSL_DIU_PORT_DLVDS: 218 clrbits8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK); 219 break; 220 } 221} 222 223/** 224 * mpc8610hpcd_set_pixel_clock: program the DIU's clock 225 * 226 * @pixclock: the wavelength, in picoseconds, of the clock 227 */ 228void mpc8610hpcd_set_pixel_clock(unsigned int pixclock) 229{ 230 struct device_node *guts_np = NULL; 231 struct ccsr_guts __iomem *guts; 232 unsigned long freq; 233 u64 temp; 234 u32 pxclk; 235 236 /* Map the global utilities registers. */ 237 guts_np = of_find_compatible_node(NULL, NULL, "fsl,mpc8610-guts"); 238 if (!guts_np) { 239 pr_err("mpc8610hpcd: missing global utilities device node\n"); 240 return; 241 } 242 243 guts = of_iomap(guts_np, 0); 244 of_node_put(guts_np); 245 if (!guts) { 246 pr_err("mpc8610hpcd: could not map global utilities device\n"); 247 return; 248 } 249 250 /* Convert pixclock from a wavelength to a frequency */ 251 temp = 1000000000000ULL; 252 do_div(temp, pixclock); 253 freq = temp; 254 255 /* 256 * 'pxclk' is the ratio of the platform clock to the pixel clock. 257 * On the MPC8610, the value programmed into CLKDVDR is the ratio 258 * minus one. The valid range of values is 2-31. 259 */ 260 pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq) - 1; 261 pxclk = clamp_t(u32, pxclk, 2, 31); 262 263 /* Disable the pixel clock, and set it to non-inverted and no delay */ 264 clrbits32(&guts->clkdvdr, 265 CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK); 266 267 /* Enable the clock and set the pxclk */ 268 setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); 269 270 iounmap(guts); 271} 272 273enum fsl_diu_monitor_port 274mpc8610hpcd_valid_monitor_port(enum fsl_diu_monitor_port port) 275{ 276 return port; 277} 278 279#endif 280 281static void __init mpc86xx_hpcd_setup_arch(void) 282{ 283 struct resource r; 284 unsigned char *pixis; 285 286 if (ppc_md.progress) 287 ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0); 288 289 fsl_pci_assign_primary(); 290 291#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) 292 diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format; 293 diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table; 294 diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port; 295 diu_ops.set_pixel_clock = mpc8610hpcd_set_pixel_clock; 296 diu_ops.valid_monitor_port = mpc8610hpcd_valid_monitor_port; 297#endif 298 299 pixis_node = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis"); 300 if (pixis_node) { 301 of_address_to_resource(pixis_node, 0, &r); 302 of_node_put(pixis_node); 303 pixis = ioremap(r.start, 32); 304 if (!pixis) { 305 printk(KERN_ERR "Err: can't map FPGA cfg register!\n"); 306 return; 307 } 308 pixis_bdcfg0 = pixis + 8; 309 pixis_arch = pixis + 1; 310 } else 311 printk(KERN_ERR "Err: " 312 "can't find device node 'fsl,fpga-pixis'\n"); 313 314 printk("MPC86xx HPCD board from Freescale Semiconductor\n"); 315} 316 317/* 318 * Called very early, device-tree isn't unflattened 319 */ 320static int __init mpc86xx_hpcd_probe(void) 321{ 322 unsigned long root = of_get_flat_dt_root(); 323 324 if (of_flat_dt_is_compatible(root, "fsl,MPC8610HPCD")) 325 return 1; /* Looks good */ 326 327 return 0; 328} 329 330static long __init mpc86xx_time_init(void) 331{ 332 unsigned int temp; 333 334 /* Set the time base to zero */ 335 mtspr(SPRN_TBWL, 0); 336 mtspr(SPRN_TBWU, 0); 337 338 temp = mfspr(SPRN_HID0); 339 temp |= HID0_TBEN; 340 mtspr(SPRN_HID0, temp); 341 asm volatile("isync"); 342 343 return 0; 344} 345 346define_machine(mpc86xx_hpcd) { 347 .name = "MPC86xx HPCD", 348 .probe = mpc86xx_hpcd_probe, 349 .setup_arch = mpc86xx_hpcd_setup_arch, 350 .init_IRQ = mpc86xx_init_irq, 351 .get_irq = mpic_get_irq, 352 .restart = fsl_rstcr_restart, 353 .time_init = mpc86xx_time_init, 354 .calibrate_decr = generic_calibrate_decr, 355 .progress = udbg_progress, 356#ifdef CONFIG_PCI 357 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 358#endif 359}; 360