1/*
2 * arch/powerpc/platforms/83xx/mpc832x_rdb.c
3 *
4 * Copyright (C) Freescale Semiconductor, Inc. 2007. All rights reserved.
5 *
6 * Description:
7 * MPC832x RDB board specific routines.
8 * This file is based on mpc832x_mds.c and mpc8313_rdb.c
9 * Author: Michael Barkowski <michael.barkowski@freescale.com>
10 *
11 * This program is free software; you can redistribute  it and/or modify it
12 * under  the terms of  the GNU General  Public License as published by the
13 * Free Software Foundation;  either version 2 of the  License, or (at your
14 * option) any later version.
15 */
16
17#include <linux/pci.h>
18#include <linux/interrupt.h>
19#include <linux/spi/spi.h>
20#include <linux/spi/mmc_spi.h>
21#include <linux/mmc/host.h>
22#include <linux/of_platform.h>
23#include <linux/fsl_devices.h>
24
25#include <asm/time.h>
26#include <asm/ipic.h>
27#include <asm/udbg.h>
28#include <asm/qe.h>
29#include <asm/qe_ic.h>
30#include <sysdev/fsl_soc.h>
31#include <sysdev/fsl_pci.h>
32
33#include "mpc83xx.h"
34
35#undef DEBUG
36#ifdef DEBUG
37#define DBG(fmt...) udbg_printf(fmt)
38#else
39#define DBG(fmt...)
40#endif
41
42#ifdef CONFIG_QUICC_ENGINE
43static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk,
44				   struct spi_board_info *board_infos,
45				   unsigned int num_board_infos,
46				   void (*cs_control)(struct spi_device *dev,
47						      bool on))
48{
49	struct device_node *np;
50	unsigned int i = 0;
51
52	for_each_compatible_node(np, type, compatible) {
53		int ret;
54		unsigned int j;
55		const void *prop;
56		struct resource res[2];
57		struct platform_device *pdev;
58		struct fsl_spi_platform_data pdata = {
59			.cs_control = cs_control,
60		};
61
62		memset(res, 0, sizeof(res));
63
64		pdata.sysclk = sysclk;
65
66		prop = of_get_property(np, "reg", NULL);
67		if (!prop)
68			goto err;
69		pdata.bus_num = *(u32 *)prop;
70
71		prop = of_get_property(np, "cell-index", NULL);
72		if (prop)
73			i = *(u32 *)prop;
74
75		prop = of_get_property(np, "mode", NULL);
76		if (prop && !strcmp(prop, "cpu-qe"))
77			pdata.flags = SPI_QE_CPU_MODE;
78
79		for (j = 0; j < num_board_infos; j++) {
80			if (board_infos[j].bus_num == pdata.bus_num)
81				pdata.max_chipselect++;
82		}
83
84		if (!pdata.max_chipselect)
85			continue;
86
87		ret = of_address_to_resource(np, 0, &res[0]);
88		if (ret)
89			goto err;
90
91		ret = of_irq_to_resource(np, 0, &res[1]);
92		if (ret == NO_IRQ)
93			goto err;
94
95		pdev = platform_device_alloc("mpc83xx_spi", i);
96		if (!pdev)
97			goto err;
98
99		ret = platform_device_add_data(pdev, &pdata, sizeof(pdata));
100		if (ret)
101			goto unreg;
102
103		ret = platform_device_add_resources(pdev, res,
104						    ARRAY_SIZE(res));
105		if (ret)
106			goto unreg;
107
108		ret = platform_device_add(pdev);
109		if (ret)
110			goto unreg;
111
112		goto next;
113unreg:
114		platform_device_del(pdev);
115err:
116		pr_err("%s: registration failed\n", np->full_name);
117next:
118		i++;
119	}
120
121	return i;
122}
123
124static int __init fsl_spi_init(struct spi_board_info *board_infos,
125			       unsigned int num_board_infos,
126			       void (*cs_control)(struct spi_device *spi,
127						  bool on))
128{
129	u32 sysclk = -1;
130	int ret;
131
132	/* SPI controller is either clocked from QE or SoC clock */
133	sysclk = get_brgfreq();
134	if (sysclk == -1) {
135		sysclk = fsl_get_sys_freq();
136		if (sysclk == -1)
137			return -ENODEV;
138	}
139
140	ret = of_fsl_spi_probe(NULL, "fsl,spi", sysclk, board_infos,
141			       num_board_infos, cs_control);
142	if (!ret)
143		of_fsl_spi_probe("spi", "fsl_spi", sysclk, board_infos,
144				 num_board_infos, cs_control);
145
146	return spi_register_board_info(board_infos, num_board_infos);
147}
148
149static void mpc83xx_spi_cs_control(struct spi_device *spi, bool on)
150{
151	pr_debug("%s %d %d\n", __func__, spi->chip_select, on);
152	par_io_data_set(3, 13, on);
153}
154
155static struct mmc_spi_platform_data mpc832x_mmc_pdata = {
156	.ocr_mask = MMC_VDD_33_34,
157};
158
159static struct spi_board_info mpc832x_spi_boardinfo = {
160	.bus_num = 0x4c0,
161	.chip_select = 0,
162	.max_speed_hz = 50000000,
163	.modalias = "mmc_spi",
164	.platform_data = &mpc832x_mmc_pdata,
165};
166
167static int __init mpc832x_spi_init(void)
168{
169	par_io_config_pin(3,  0, 3, 0, 1, 0); /* SPI1 MOSI, I/O */
170	par_io_config_pin(3,  1, 3, 0, 1, 0); /* SPI1 MISO, I/O */
171	par_io_config_pin(3,  2, 3, 0, 1, 0); /* SPI1 CLK,  I/O */
172	par_io_config_pin(3,  3, 2, 0, 1, 0); /* SPI1 SEL,  I   */
173
174	par_io_config_pin(3, 13, 1, 0, 0, 0); /* !SD_CS,    O */
175	par_io_config_pin(3, 14, 2, 0, 0, 0); /* SD_INSERT, I */
176	par_io_config_pin(3, 15, 2, 0, 0, 0); /* SD_PROTECT,I */
177
178	/*
179	 * Don't bother with legacy stuff when device tree contains
180	 * mmc-spi-slot node.
181	 */
182	if (of_find_compatible_node(NULL, NULL, "mmc-spi-slot"))
183		return 0;
184	return fsl_spi_init(&mpc832x_spi_boardinfo, 1, mpc83xx_spi_cs_control);
185}
186machine_device_initcall(mpc832x_rdb, mpc832x_spi_init);
187#endif /* CONFIG_QUICC_ENGINE */
188
189/* ************************************************************************
190 *
191 * Setup the architecture
192 *
193 */
194static void __init mpc832x_rdb_setup_arch(void)
195{
196#if defined(CONFIG_QUICC_ENGINE)
197	struct device_node *np;
198#endif
199
200	if (ppc_md.progress)
201		ppc_md.progress("mpc832x_rdb_setup_arch()", 0);
202
203	mpc83xx_setup_pci();
204
205#ifdef CONFIG_QUICC_ENGINE
206	qe_reset();
207
208	if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
209		par_io_init(np);
210		of_node_put(np);
211
212		for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
213			par_io_of_config(np);
214	}
215#endif				/* CONFIG_QUICC_ENGINE */
216}
217
218machine_device_initcall(mpc832x_rdb, mpc83xx_declare_of_platform_devices);
219
220/*
221 * Called very early, MMU is off, device-tree isn't unflattened
222 */
223static int __init mpc832x_rdb_probe(void)
224{
225	unsigned long root = of_get_flat_dt_root();
226
227	return of_flat_dt_is_compatible(root, "MPC832xRDB");
228}
229
230define_machine(mpc832x_rdb) {
231	.name		= "MPC832x RDB",
232	.probe		= mpc832x_rdb_probe,
233	.setup_arch	= mpc832x_rdb_setup_arch,
234	.init_IRQ	= mpc83xx_ipic_and_qe_init_IRQ,
235	.get_irq	= ipic_get_irq,
236	.restart	= mpc83xx_restart,
237	.time_init	= mpc83xx_time_init,
238	.calibrate_decr	= generic_calibrate_decr,
239	.progress	= udbg_progress,
240};
241