1/* 2 * Copyright (C) 2001 Dave Engebretsen, IBM Corporation 3 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 4 * 5 * RTAS specific routines for PCI. 6 * 7 * Based on code from pci.c, chrp_pci.c and pSeries_pci.c 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 */ 23 24#include <linux/kernel.h> 25#include <linux/threads.h> 26#include <linux/pci.h> 27#include <linux/string.h> 28#include <linux/init.h> 29 30#include <asm/io.h> 31#include <asm/pgtable.h> 32#include <asm/irq.h> 33#include <asm/prom.h> 34#include <asm/machdep.h> 35#include <asm/pci-bridge.h> 36#include <asm/iommu.h> 37#include <asm/rtas.h> 38#include <asm/mpic.h> 39#include <asm/ppc-pci.h> 40#include <asm/eeh.h> 41 42/* RTAS tokens */ 43static int read_pci_config; 44static int write_pci_config; 45static int ibm_read_pci_config; 46static int ibm_write_pci_config; 47 48static inline int config_access_valid(struct pci_dn *dn, int where) 49{ 50 if (where < 256) 51 return 1; 52 if (where < 4096 && dn->pci_ext_config_space) 53 return 1; 54 55 return 0; 56} 57 58int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val) 59{ 60 int returnval = -1; 61 unsigned long buid, addr; 62 int ret; 63 64 if (!pdn) 65 return PCIBIOS_DEVICE_NOT_FOUND; 66 if (!config_access_valid(pdn, where)) 67 return PCIBIOS_BAD_REGISTER_NUMBER; 68#ifdef CONFIG_EEH 69 if (pdn->edev && pdn->edev->pe && 70 (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED)) 71 return PCIBIOS_SET_FAILED; 72#endif 73 74 addr = rtas_config_addr(pdn->busno, pdn->devfn, where); 75 buid = pdn->phb->buid; 76 if (buid) { 77 ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval, 78 addr, BUID_HI(buid), BUID_LO(buid), size); 79 } else { 80 ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size); 81 } 82 *val = returnval; 83 84 if (ret) 85 return PCIBIOS_DEVICE_NOT_FOUND; 86 87 return PCIBIOS_SUCCESSFUL; 88} 89 90static int rtas_pci_read_config(struct pci_bus *bus, 91 unsigned int devfn, 92 int where, int size, u32 *val) 93{ 94 struct device_node *busdn, *dn; 95 struct pci_dn *pdn; 96 bool found = false; 97 int ret; 98 99 /* Search only direct children of the bus */ 100 *val = 0xFFFFFFFF; 101 busdn = pci_bus_to_OF_node(bus); 102 for (dn = busdn->child; dn; dn = dn->sibling) { 103 pdn = PCI_DN(dn); 104 if (pdn && pdn->devfn == devfn 105 && of_device_is_available(dn)) { 106 found = true; 107 break; 108 } 109 } 110 111 if (!found) 112 return PCIBIOS_DEVICE_NOT_FOUND; 113 114 ret = rtas_read_config(pdn, where, size, val); 115 if (*val == EEH_IO_ERROR_VALUE(size) && 116 eeh_dev_check_failure(pdn_to_eeh_dev(pdn))) 117 return PCIBIOS_DEVICE_NOT_FOUND; 118 119 return ret; 120} 121 122int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val) 123{ 124 unsigned long buid, addr; 125 int ret; 126 127 if (!pdn) 128 return PCIBIOS_DEVICE_NOT_FOUND; 129 if (!config_access_valid(pdn, where)) 130 return PCIBIOS_BAD_REGISTER_NUMBER; 131#ifdef CONFIG_EEH 132 if (pdn->edev && pdn->edev->pe && 133 (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED)) 134 return PCIBIOS_SET_FAILED; 135#endif 136 137 addr = rtas_config_addr(pdn->busno, pdn->devfn, where); 138 buid = pdn->phb->buid; 139 if (buid) { 140 ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr, 141 BUID_HI(buid), BUID_LO(buid), size, (ulong) val); 142 } else { 143 ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val); 144 } 145 146 if (ret) 147 return PCIBIOS_DEVICE_NOT_FOUND; 148 149 return PCIBIOS_SUCCESSFUL; 150} 151 152static int rtas_pci_write_config(struct pci_bus *bus, 153 unsigned int devfn, 154 int where, int size, u32 val) 155{ 156 struct device_node *busdn, *dn; 157 struct pci_dn *pdn; 158 bool found = false; 159 160 /* Search only direct children of the bus */ 161 busdn = pci_bus_to_OF_node(bus); 162 for (dn = busdn->child; dn; dn = dn->sibling) { 163 pdn = PCI_DN(dn); 164 if (pdn && pdn->devfn == devfn 165 && of_device_is_available(dn)) { 166 found = true; 167 break; 168 } 169 } 170 171 if (!found) 172 return PCIBIOS_DEVICE_NOT_FOUND; 173 174 return rtas_write_config(pdn, where, size, val); 175} 176 177static struct pci_ops rtas_pci_ops = { 178 .read = rtas_pci_read_config, 179 .write = rtas_pci_write_config, 180}; 181 182static int is_python(struct device_node *dev) 183{ 184 const char *model = of_get_property(dev, "model", NULL); 185 186 if (model && strstr(model, "Python")) 187 return 1; 188 189 return 0; 190} 191 192static void python_countermeasures(struct device_node *dev) 193{ 194 struct resource registers; 195 void __iomem *chip_regs; 196 volatile u32 val; 197 198 if (of_address_to_resource(dev, 0, ®isters)) { 199 printk(KERN_ERR "Can't get address for Python workarounds !\n"); 200 return; 201 } 202 203 /* Python's register file is 1 MB in size. */ 204 chip_regs = ioremap(registers.start & ~(0xfffffUL), 0x100000); 205 206 /* 207 * Firmware doesn't always clear this bit which is critical 208 * for good performance - Anton 209 */ 210 211#define PRG_CL_RESET_VALID 0x00010000 212 213 val = in_be32(chip_regs + 0xf6030); 214 if (val & PRG_CL_RESET_VALID) { 215 printk(KERN_INFO "Python workaround: "); 216 val &= ~PRG_CL_RESET_VALID; 217 out_be32(chip_regs + 0xf6030, val); 218 /* 219 * We must read it back for changes to 220 * take effect 221 */ 222 val = in_be32(chip_regs + 0xf6030); 223 printk("reg0: %x\n", val); 224 } 225 226 iounmap(chip_regs); 227} 228 229void __init init_pci_config_tokens(void) 230{ 231 read_pci_config = rtas_token("read-pci-config"); 232 write_pci_config = rtas_token("write-pci-config"); 233 ibm_read_pci_config = rtas_token("ibm,read-pci-config"); 234 ibm_write_pci_config = rtas_token("ibm,write-pci-config"); 235} 236 237unsigned long get_phb_buid(struct device_node *phb) 238{ 239 struct resource r; 240 241 if (ibm_read_pci_config == -1) 242 return 0; 243 if (of_address_to_resource(phb, 0, &r)) 244 return 0; 245 return r.start; 246} 247 248static int phb_set_bus_ranges(struct device_node *dev, 249 struct pci_controller *phb) 250{ 251 const __be32 *bus_range; 252 unsigned int len; 253 254 bus_range = of_get_property(dev, "bus-range", &len); 255 if (bus_range == NULL || len < 2 * sizeof(int)) { 256 return 1; 257 } 258 259 phb->first_busno = be32_to_cpu(bus_range[0]); 260 phb->last_busno = be32_to_cpu(bus_range[1]); 261 262 return 0; 263} 264 265int rtas_setup_phb(struct pci_controller *phb) 266{ 267 struct device_node *dev = phb->dn; 268 269 if (is_python(dev)) 270 python_countermeasures(dev); 271 272 if (phb_set_bus_ranges(dev, phb)) 273 return 1; 274 275 phb->ops = &rtas_pci_ops; 276 phb->buid = get_phb_buid(dev); 277 278 return 0; 279} 280