1#ifndef _ASM_POWERPC_PGTABLE_PPC64_64K_H 2#define _ASM_POWERPC_PGTABLE_PPC64_64K_H 3 4#include <asm-generic/pgtable-nopud.h> 5 6 7#define PTE_INDEX_SIZE 8 8#define PMD_INDEX_SIZE 10 9#define PUD_INDEX_SIZE 0 10#define PGD_INDEX_SIZE 12 11 12#ifndef __ASSEMBLY__ 13#define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE) 14#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE) 15#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) 16#endif /* __ASSEMBLY__ */ 17 18#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 19#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 20#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 21 22/* With 4k base page size, hugepage PTEs go at the PMD level */ 23#define MIN_HUGEPTE_SHIFT PAGE_SHIFT 24 25/* PMD_SHIFT determines what a second-level page table entry can map */ 26#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 27#define PMD_SIZE (1UL << PMD_SHIFT) 28#define PMD_MASK (~(PMD_SIZE-1)) 29 30/* PGDIR_SHIFT determines what a third-level page table entry can map */ 31#define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 32#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 33#define PGDIR_MASK (~(PGDIR_SIZE-1)) 34 35/* Bits to mask out from a PMD to get to the PTE page */ 36/* PMDs point to PTE table fragments which are 4K aligned. */ 37#define PMD_MASKED_BITS 0xfff 38/* Bits to mask out from a PGD/PUD to get to the PMD page */ 39#define PUD_MASKED_BITS 0x1ff 40 41#define pgd_pte(pgd) (pud_pte(((pud_t){ pgd }))) 42#define pte_pgd(pte) ((pgd_t)pte_pud(pte)) 43 44#endif /* _ASM_POWERPC_PGTABLE_PPC64_64K_H */ 45