1#ifndef _PARISC_PGTABLE_H 2#define _PARISC_PGTABLE_H 3 4#include <asm-generic/4level-fixup.h> 5 6#include <asm/fixmap.h> 7 8#ifndef __ASSEMBLY__ 9/* 10 * we simulate an x86-style page table for the linux mm code 11 */ 12 13#include <linux/bitops.h> 14#include <linux/spinlock.h> 15#include <linux/mm_types.h> 16#include <asm/processor.h> 17#include <asm/cache.h> 18 19extern spinlock_t pa_tlb_lock; 20 21/* 22 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel 23 * memory. For the return value to be meaningful, ADDR must be >= 24 * PAGE_OFFSET. This operation can be relatively expensive (e.g., 25 * require a hash-, or multi-level tree-lookup or something of that 26 * sort) but it guarantees to return TRUE only if accessing the page 27 * at that address does not cause an error. Note that there may be 28 * addresses for which kern_addr_valid() returns FALSE even though an 29 * access would not cause an error (e.g., this is typically true for 30 * memory mapped I/O regions. 31 * 32 * XXX Need to implement this for parisc. 33 */ 34#define kern_addr_valid(addr) (1) 35 36/* Purge data and instruction TLB entries. Must be called holding 37 * the pa_tlb_lock. The TLB purge instructions are slow on SMP 38 * machines since the purge must be broadcast to all CPUs. 39 */ 40 41static inline void purge_tlb_entries(struct mm_struct *mm, unsigned long addr) 42{ 43 mtsp(mm->context, 1); 44 pdtlb(addr); 45 if (unlikely(split_tlb)) 46 pitlb(addr); 47} 48 49/* Certain architectures need to do special things when PTEs 50 * within a page table are directly modified. Thus, the following 51 * hook is made available. 52 */ 53#define set_pte(pteptr, pteval) \ 54 do{ \ 55 *(pteptr) = (pteval); \ 56 } while(0) 57 58#define pte_inserted(x) \ 59 ((pte_val(x) & (_PAGE_PRESENT|_PAGE_ACCESSED)) \ 60 == (_PAGE_PRESENT|_PAGE_ACCESSED)) 61 62#define set_pte_at(mm, addr, ptep, pteval) \ 63 do { \ 64 pte_t old_pte; \ 65 unsigned long flags; \ 66 spin_lock_irqsave(&pa_tlb_lock, flags); \ 67 old_pte = *ptep; \ 68 set_pte(ptep, pteval); \ 69 if (pte_inserted(old_pte)) \ 70 purge_tlb_entries(mm, addr); \ 71 spin_unlock_irqrestore(&pa_tlb_lock, flags); \ 72 } while (0) 73 74#endif /* !__ASSEMBLY__ */ 75 76#include <asm/page.h> 77 78#define pte_ERROR(e) \ 79 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 80#define pmd_ERROR(e) \ 81 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e)) 82#define pgd_ERROR(e) \ 83 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e)) 84 85/* This is the size of the initially mapped kernel memory */ 86#define KERNEL_INITIAL_ORDER 24 /* 0 to 1<<24 = 16MB */ 87#define KERNEL_INITIAL_SIZE (1 << KERNEL_INITIAL_ORDER) 88 89#if CONFIG_PGTABLE_LEVELS == 3 90#define PGD_ORDER 1 /* Number of pages per pgd */ 91#define PMD_ORDER 1 /* Number of pages per pmd */ 92#define PGD_ALLOC_ORDER 2 /* first pgd contains pmd */ 93#else 94#define PGD_ORDER 1 /* Number of pages per pgd */ 95#define PGD_ALLOC_ORDER PGD_ORDER 96#endif 97 98/* Definitions for 3rd level (we use PLD here for Page Lower directory 99 * because PTE_SHIFT is used lower down to mean shift that has to be 100 * done to get usable bits out of the PTE) */ 101#define PLD_SHIFT PAGE_SHIFT 102#define PLD_SIZE PAGE_SIZE 103#define BITS_PER_PTE (PAGE_SHIFT - BITS_PER_PTE_ENTRY) 104#define PTRS_PER_PTE (1UL << BITS_PER_PTE) 105 106/* Definitions for 2nd level */ 107#define pgtable_cache_init() do { } while (0) 108 109#define PMD_SHIFT (PLD_SHIFT + BITS_PER_PTE) 110#define PMD_SIZE (1UL << PMD_SHIFT) 111#define PMD_MASK (~(PMD_SIZE-1)) 112#if CONFIG_PGTABLE_LEVELS == 3 113#define BITS_PER_PMD (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY) 114#else 115#define __PAGETABLE_PMD_FOLDED 116#define BITS_PER_PMD 0 117#endif 118#define PTRS_PER_PMD (1UL << BITS_PER_PMD) 119 120/* Definitions for 1st level */ 121#define PGDIR_SHIFT (PMD_SHIFT + BITS_PER_PMD) 122#if (PGDIR_SHIFT + PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY) > BITS_PER_LONG 123#define BITS_PER_PGD (BITS_PER_LONG - PGDIR_SHIFT) 124#else 125#define BITS_PER_PGD (PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY) 126#endif 127#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 128#define PGDIR_MASK (~(PGDIR_SIZE-1)) 129#define PTRS_PER_PGD (1UL << BITS_PER_PGD) 130#define USER_PTRS_PER_PGD PTRS_PER_PGD 131 132#ifdef CONFIG_64BIT 133#define MAX_ADDRBITS (PGDIR_SHIFT + BITS_PER_PGD) 134#define MAX_ADDRESS (1UL << MAX_ADDRBITS) 135#define SPACEID_SHIFT (MAX_ADDRBITS - 32) 136#else 137#define MAX_ADDRBITS (BITS_PER_LONG) 138#define MAX_ADDRESS (1UL << MAX_ADDRBITS) 139#define SPACEID_SHIFT 0 140#endif 141 142/* This calculates the number of initial pages we need for the initial 143 * page tables */ 144#if (KERNEL_INITIAL_ORDER) >= (PMD_SHIFT) 145# define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT)) 146#else 147# define PT_INITIAL (1) /* all initial PTEs fit into one page */ 148#endif 149 150/* 151 * pgd entries used up by user/kernel: 152 */ 153 154#define FIRST_USER_ADDRESS 0UL 155 156/* NB: The tlb miss handlers make certain assumptions about the order */ 157/* of the following bits, so be careful (One example, bits 25-31 */ 158/* are moved together in one instruction). */ 159 160#define _PAGE_READ_BIT 31 /* (0x001) read access allowed */ 161#define _PAGE_WRITE_BIT 30 /* (0x002) write access allowed */ 162#define _PAGE_EXEC_BIT 29 /* (0x004) execute access allowed */ 163#define _PAGE_GATEWAY_BIT 28 /* (0x008) privilege promotion allowed */ 164#define _PAGE_DMB_BIT 27 /* (0x010) Data Memory Break enable (B bit) */ 165#define _PAGE_DIRTY_BIT 26 /* (0x020) Page Dirty (D bit) */ 166#define _PAGE_REFTRAP_BIT 25 /* (0x040) Page Ref. Trap enable (T bit) */ 167#define _PAGE_NO_CACHE_BIT 24 /* (0x080) Uncached Page (U bit) */ 168#define _PAGE_ACCESSED_BIT 23 /* (0x100) Software: Page Accessed */ 169#define _PAGE_PRESENT_BIT 22 /* (0x200) Software: translation valid */ 170/* bit 21 was formerly the FLUSH bit but is now unused */ 171#define _PAGE_USER_BIT 20 /* (0x800) Software: User accessible page */ 172 173/* N.B. The bits are defined in terms of a 32 bit word above, so the */ 174/* following macro is ok for both 32 and 64 bit. */ 175 176#define xlate_pabit(x) (31 - x) 177 178/* this defines the shift to the usable bits in the PTE it is set so 179 * that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set 180 * to zero */ 181#define PTE_SHIFT xlate_pabit(_PAGE_USER_BIT) 182 183/* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */ 184#define PFN_PTE_SHIFT 12 185 186#define _PAGE_READ (1 << xlate_pabit(_PAGE_READ_BIT)) 187#define _PAGE_WRITE (1 << xlate_pabit(_PAGE_WRITE_BIT)) 188#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 189#define _PAGE_EXEC (1 << xlate_pabit(_PAGE_EXEC_BIT)) 190#define _PAGE_GATEWAY (1 << xlate_pabit(_PAGE_GATEWAY_BIT)) 191#define _PAGE_DMB (1 << xlate_pabit(_PAGE_DMB_BIT)) 192#define _PAGE_DIRTY (1 << xlate_pabit(_PAGE_DIRTY_BIT)) 193#define _PAGE_REFTRAP (1 << xlate_pabit(_PAGE_REFTRAP_BIT)) 194#define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT)) 195#define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT)) 196#define _PAGE_PRESENT (1 << xlate_pabit(_PAGE_PRESENT_BIT)) 197#define _PAGE_USER (1 << xlate_pabit(_PAGE_USER_BIT)) 198 199#define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED) 200#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) 201#define _PAGE_KERNEL_RO (_PAGE_PRESENT | _PAGE_READ | _PAGE_DIRTY | _PAGE_ACCESSED) 202#define _PAGE_KERNEL_EXEC (_PAGE_KERNEL_RO | _PAGE_EXEC) 203#define _PAGE_KERNEL_RWX (_PAGE_KERNEL_EXEC | _PAGE_WRITE) 204#define _PAGE_KERNEL (_PAGE_KERNEL_RO | _PAGE_WRITE) 205 206/* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds 207 * are page-aligned, we don't care about the PAGE_OFFSET bits, except 208 * for a few meta-information bits, so we shift the address to be 209 * able to effectively address 40/42/44-bits of physical address space 210 * depending on 4k/16k/64k PAGE_SIZE */ 211#define _PxD_PRESENT_BIT 31 212#define _PxD_ATTACHED_BIT 30 213#define _PxD_VALID_BIT 29 214 215#define PxD_FLAG_PRESENT (1 << xlate_pabit(_PxD_PRESENT_BIT)) 216#define PxD_FLAG_ATTACHED (1 << xlate_pabit(_PxD_ATTACHED_BIT)) 217#define PxD_FLAG_VALID (1 << xlate_pabit(_PxD_VALID_BIT)) 218#define PxD_FLAG_MASK (0xf) 219#define PxD_FLAG_SHIFT (4) 220#define PxD_VALUE_SHIFT (8) /* (PAGE_SHIFT-PxD_FLAG_SHIFT) */ 221 222#ifndef __ASSEMBLY__ 223 224#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED) 225#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_ACCESSED) 226/* Others seem to make this executable, I don't know if that's correct 227 or not. The stack is mapped this way though so this is necessary 228 in the short term - dhd@linuxcare.com, 2000-08-08 */ 229#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_ACCESSED) 230#define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITE | _PAGE_ACCESSED) 231#define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_EXEC |_PAGE_ACCESSED) 232#define PAGE_COPY PAGE_EXECREAD 233#define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC |_PAGE_ACCESSED) 234#define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 235#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL_EXEC) 236#define PAGE_KERNEL_RWX __pgprot(_PAGE_KERNEL_RWX) 237#define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL_RO) 238#define PAGE_KERNEL_UNC __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE) 239#define PAGE_GATEWAY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_GATEWAY| _PAGE_READ) 240 241 242/* 243 * We could have an execute only page using "gateway - promote to priv 244 * level 3", but that is kind of silly. So, the way things are defined 245 * now, we must always have read permission for pages with execute 246 * permission. For the fun of it we'll go ahead and support write only 247 * pages. 248 */ 249 250 /*xwr*/ 251#define __P000 PAGE_NONE 252#define __P001 PAGE_READONLY 253#define __P010 __P000 /* copy on write */ 254#define __P011 __P001 /* copy on write */ 255#define __P100 PAGE_EXECREAD 256#define __P101 PAGE_EXECREAD 257#define __P110 __P100 /* copy on write */ 258#define __P111 __P101 /* copy on write */ 259 260#define __S000 PAGE_NONE 261#define __S001 PAGE_READONLY 262#define __S010 PAGE_WRITEONLY 263#define __S011 PAGE_SHARED 264#define __S100 PAGE_EXECREAD 265#define __S101 PAGE_EXECREAD 266#define __S110 PAGE_RWX 267#define __S111 PAGE_RWX 268 269 270extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */ 271 272/* initial page tables for 0-8MB for kernel */ 273 274extern pte_t pg0[]; 275 276/* zero page used for uninitialized stuff */ 277 278extern unsigned long *empty_zero_page; 279 280/* 281 * ZERO_PAGE is a global shared page that is always zero: used 282 * for zero-mapped memory areas etc.. 283 */ 284 285#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 286 287#define pte_none(x) (pte_val(x) == 0) 288#define pte_present(x) (pte_val(x) & _PAGE_PRESENT) 289#define pte_clear(mm, addr, xp) set_pte_at(mm, addr, xp, __pte(0)) 290 291#define pmd_flag(x) (pmd_val(x) & PxD_FLAG_MASK) 292#define pmd_address(x) ((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT) 293#define pgd_flag(x) (pgd_val(x) & PxD_FLAG_MASK) 294#define pgd_address(x) ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT) 295 296#if CONFIG_PGTABLE_LEVELS == 3 297/* The first entry of the permanent pmd is not there if it contains 298 * the gateway marker */ 299#define pmd_none(x) (!pmd_val(x) || pmd_flag(x) == PxD_FLAG_ATTACHED) 300#else 301#define pmd_none(x) (!pmd_val(x)) 302#endif 303#define pmd_bad(x) (!(pmd_flag(x) & PxD_FLAG_VALID)) 304#define pmd_present(x) (pmd_flag(x) & PxD_FLAG_PRESENT) 305static inline void pmd_clear(pmd_t *pmd) { 306#if CONFIG_PGTABLE_LEVELS == 3 307 if (pmd_flag(*pmd) & PxD_FLAG_ATTACHED) 308 /* This is the entry pointing to the permanent pmd 309 * attached to the pgd; cannot clear it */ 310 __pmd_val_set(*pmd, PxD_FLAG_ATTACHED); 311 else 312#endif 313 __pmd_val_set(*pmd, 0); 314} 315 316 317 318#if CONFIG_PGTABLE_LEVELS == 3 319#define pgd_page_vaddr(pgd) ((unsigned long) __va(pgd_address(pgd))) 320#define pgd_page(pgd) virt_to_page((void *)pgd_page_vaddr(pgd)) 321 322/* For 64 bit we have three level tables */ 323 324#define pgd_none(x) (!pgd_val(x)) 325#define pgd_bad(x) (!(pgd_flag(x) & PxD_FLAG_VALID)) 326#define pgd_present(x) (pgd_flag(x) & PxD_FLAG_PRESENT) 327static inline void pgd_clear(pgd_t *pgd) { 328#if CONFIG_PGTABLE_LEVELS == 3 329 if(pgd_flag(*pgd) & PxD_FLAG_ATTACHED) 330 /* This is the permanent pmd attached to the pgd; cannot 331 * free it */ 332 return; 333#endif 334 __pgd_val_set(*pgd, 0); 335} 336#else 337/* 338 * The "pgd_xxx()" functions here are trivial for a folded two-level 339 * setup: the pgd is never bad, and a pmd always exists (as it's folded 340 * into the pgd entry) 341 */ 342static inline int pgd_none(pgd_t pgd) { return 0; } 343static inline int pgd_bad(pgd_t pgd) { return 0; } 344static inline int pgd_present(pgd_t pgd) { return 1; } 345static inline void pgd_clear(pgd_t * pgdp) { } 346#endif 347 348/* 349 * The following only work if pte_present() is true. 350 * Undefined behaviour if not.. 351 */ 352static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } 353static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } 354static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } 355static inline int pte_special(pte_t pte) { return 0; } 356 357static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; } 358static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } 359static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_WRITE; return pte; } 360static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; } 361static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; } 362static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return pte; } 363static inline pte_t pte_mkspecial(pte_t pte) { return pte; } 364 365/* 366 * Conversion functions: convert a page and protection to a page entry, 367 * and a page entry and page directory to the page they refer to. 368 */ 369#define __mk_pte(addr,pgprot) \ 370({ \ 371 pte_t __pte; \ 372 \ 373 pte_val(__pte) = ((((addr)>>PAGE_SHIFT)<<PFN_PTE_SHIFT) + pgprot_val(pgprot)); \ 374 \ 375 __pte; \ 376}) 377 378#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 379 380static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 381{ 382 pte_t pte; 383 pte_val(pte) = (pfn << PFN_PTE_SHIFT) | pgprot_val(pgprot); 384 return pte; 385} 386 387static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 388{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; } 389 390/* Permanent address of a page. On parisc we don't have highmem. */ 391 392#define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT) 393 394#define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 395 396#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_address(pmd))) 397 398#define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd))) 399#define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) 400 401#define pgd_index(address) ((address) >> PGDIR_SHIFT) 402 403/* to find an entry in a page-table-directory */ 404#define pgd_offset(mm, address) \ 405((mm)->pgd + ((address) >> PGDIR_SHIFT)) 406 407/* to find an entry in a kernel page-table-directory */ 408#define pgd_offset_k(address) pgd_offset(&init_mm, address) 409 410/* Find an entry in the second-level page table.. */ 411 412#if CONFIG_PGTABLE_LEVELS == 3 413#define pmd_offset(dir,address) \ 414((pmd_t *) pgd_page_vaddr(*(dir)) + (((address)>>PMD_SHIFT) & (PTRS_PER_PMD-1))) 415#else 416#define pmd_offset(dir,addr) ((pmd_t *) dir) 417#endif 418 419/* Find an entry in the third-level page table.. */ 420#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) 421#define pte_offset_kernel(pmd, address) \ 422 ((pte_t *) pmd_page_vaddr(*(pmd)) + pte_index(address)) 423#define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) 424#define pte_unmap(pte) do { } while (0) 425 426#define pte_unmap(pte) do { } while (0) 427#define pte_unmap_nested(pte) do { } while (0) 428 429extern void paging_init (void); 430 431/* Used for deferring calls to flush_dcache_page() */ 432 433#define PG_dcache_dirty PG_arch_1 434 435extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); 436 437/* Encode and de-code a swap entry */ 438 439#define __swp_type(x) ((x).val & 0x1f) 440#define __swp_offset(x) ( (((x).val >> 6) & 0x7) | \ 441 (((x).val >> 8) & ~0x7) ) 442#define __swp_entry(type, offset) ((swp_entry_t) { (type) | \ 443 ((offset & 0x7) << 6) | \ 444 ((offset & ~0x7) << 8) }) 445#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 446#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 447 448static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep) 449{ 450 pte_t pte; 451 unsigned long flags; 452 453 if (!pte_young(*ptep)) 454 return 0; 455 456 spin_lock_irqsave(&pa_tlb_lock, flags); 457 pte = *ptep; 458 if (!pte_young(pte)) { 459 spin_unlock_irqrestore(&pa_tlb_lock, flags); 460 return 0; 461 } 462 set_pte(ptep, pte_mkold(pte)); 463 purge_tlb_entries(vma->vm_mm, addr); 464 spin_unlock_irqrestore(&pa_tlb_lock, flags); 465 return 1; 466} 467 468struct mm_struct; 469static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 470{ 471 pte_t old_pte; 472 unsigned long flags; 473 474 spin_lock_irqsave(&pa_tlb_lock, flags); 475 old_pte = *ptep; 476 set_pte(ptep, __pte(0)); 477 if (pte_inserted(old_pte)) 478 purge_tlb_entries(mm, addr); 479 spin_unlock_irqrestore(&pa_tlb_lock, flags); 480 481 return old_pte; 482} 483 484static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 485{ 486 unsigned long flags; 487 spin_lock_irqsave(&pa_tlb_lock, flags); 488 set_pte(ptep, pte_wrprotect(*ptep)); 489 purge_tlb_entries(mm, addr); 490 spin_unlock_irqrestore(&pa_tlb_lock, flags); 491} 492 493#define pte_same(A,B) (pte_val(A) == pte_val(B)) 494 495#endif /* !__ASSEMBLY__ */ 496 497 498/* TLB page size encoding - see table 3-1 in parisc20.pdf */ 499#define _PAGE_SIZE_ENCODING_4K 0 500#define _PAGE_SIZE_ENCODING_16K 1 501#define _PAGE_SIZE_ENCODING_64K 2 502#define _PAGE_SIZE_ENCODING_256K 3 503#define _PAGE_SIZE_ENCODING_1M 4 504#define _PAGE_SIZE_ENCODING_4M 5 505#define _PAGE_SIZE_ENCODING_16M 6 506#define _PAGE_SIZE_ENCODING_64M 7 507 508#if defined(CONFIG_PARISC_PAGE_SIZE_4KB) 509# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_4K 510#elif defined(CONFIG_PARISC_PAGE_SIZE_16KB) 511# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_16K 512#elif defined(CONFIG_PARISC_PAGE_SIZE_64KB) 513# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_64K 514#endif 515 516 517#define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE) 518 519/* We provide our own get_unmapped_area to provide cache coherency */ 520 521#define HAVE_ARCH_UNMAPPED_AREA 522#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 523 524#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 525#define __HAVE_ARCH_PTEP_GET_AND_CLEAR 526#define __HAVE_ARCH_PTEP_SET_WRPROTECT 527#define __HAVE_ARCH_PTE_SAME 528#include <asm-generic/pgtable.h> 529 530#endif /* _PARISC_PGTABLE_H */ 531