1/*
2 * Toshiba RBTX4938 specific interrupt handlers
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12
13/*
14 * MIPS_CPU_IRQ_BASE+00 Software 0
15 * MIPS_CPU_IRQ_BASE+01 Software 1
16 * MIPS_CPU_IRQ_BASE+02 Cascade TX4938-CP0
17 * MIPS_CPU_IRQ_BASE+03 Multiplexed -- do not use
18 * MIPS_CPU_IRQ_BASE+04 Multiplexed -- do not use
19 * MIPS_CPU_IRQ_BASE+05 Multiplexed -- do not use
20 * MIPS_CPU_IRQ_BASE+06 Multiplexed -- do not use
21 * MIPS_CPU_IRQ_BASE+07 CPU TIMER
22 *
23 * TXX9_IRQ_BASE+00
24 * TXX9_IRQ_BASE+01
25 * TXX9_IRQ_BASE+02 Cascade RBTX4938-IOC
26 * TXX9_IRQ_BASE+03 RBTX4938 RTL-8019AS Ethernet
27 * TXX9_IRQ_BASE+04
28 * TXX9_IRQ_BASE+05 TX4938 ETH1
29 * TXX9_IRQ_BASE+06 TX4938 ETH0
30 * TXX9_IRQ_BASE+07
31 * TXX9_IRQ_BASE+08 TX4938 SIO 0
32 * TXX9_IRQ_BASE+09 TX4938 SIO 1
33 * TXX9_IRQ_BASE+10 TX4938 DMA0
34 * TXX9_IRQ_BASE+11 TX4938 DMA1
35 * TXX9_IRQ_BASE+12 TX4938 DMA2
36 * TXX9_IRQ_BASE+13 TX4938 DMA3
37 * TXX9_IRQ_BASE+14
38 * TXX9_IRQ_BASE+15
39 * TXX9_IRQ_BASE+16 TX4938 PCIC
40 * TXX9_IRQ_BASE+17 TX4938 TMR0
41 * TXX9_IRQ_BASE+18 TX4938 TMR1
42 * TXX9_IRQ_BASE+19 TX4938 TMR2
43 * TXX9_IRQ_BASE+20
44 * TXX9_IRQ_BASE+21
45 * TXX9_IRQ_BASE+22 TX4938 PCIERR
46 * TXX9_IRQ_BASE+23
47 * TXX9_IRQ_BASE+24
48 * TXX9_IRQ_BASE+25
49 * TXX9_IRQ_BASE+26
50 * TXX9_IRQ_BASE+27
51 * TXX9_IRQ_BASE+28
52 * TXX9_IRQ_BASE+29
53 * TXX9_IRQ_BASE+30
54 * TXX9_IRQ_BASE+31 TX4938 SPI
55 *
56 * RBTX4938_IRQ_IOC+00 PCI-D
57 * RBTX4938_IRQ_IOC+01 PCI-C
58 * RBTX4938_IRQ_IOC+02 PCI-B
59 * RBTX4938_IRQ_IOC+03 PCI-A
60 * RBTX4938_IRQ_IOC+04 RTC
61 * RBTX4938_IRQ_IOC+05 ATA
62 * RBTX4938_IRQ_IOC+06 MODEM
63 * RBTX4938_IRQ_IOC+07 SWINT
64 */
65#include <linux/init.h>
66#include <linux/interrupt.h>
67#include <linux/irq.h>
68#include <asm/mipsregs.h>
69#include <asm/txx9/generic.h>
70#include <asm/txx9/rbtx4938.h>
71
72static int toshiba_rbtx4938_irq_nested(int sw_irq)
73{
74	u8 level3;
75
76	level3 = readb(rbtx4938_imstat_addr);
77	if (unlikely(!level3))
78		return -1;
79	/* must use fls so onboard ATA has priority */
80	return RBTX4938_IRQ_IOC + __fls8(level3);
81}
82
83static void toshiba_rbtx4938_irq_ioc_enable(struct irq_data *d)
84{
85	unsigned char v;
86
87	v = readb(rbtx4938_imask_addr);
88	v |= (1 << (d->irq - RBTX4938_IRQ_IOC));
89	writeb(v, rbtx4938_imask_addr);
90	mmiowb();
91}
92
93static void toshiba_rbtx4938_irq_ioc_disable(struct irq_data *d)
94{
95	unsigned char v;
96
97	v = readb(rbtx4938_imask_addr);
98	v &= ~(1 << (d->irq - RBTX4938_IRQ_IOC));
99	writeb(v, rbtx4938_imask_addr);
100	mmiowb();
101}
102
103#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
104static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
105	.name = TOSHIBA_RBTX4938_IOC_NAME,
106	.irq_mask = toshiba_rbtx4938_irq_ioc_disable,
107	.irq_unmask = toshiba_rbtx4938_irq_ioc_enable,
108};
109
110static int rbtx4938_irq_dispatch(int pending)
111{
112	int irq;
113
114	if (pending & STATUSF_IP7)
115		irq = MIPS_CPU_IRQ_BASE + 7;
116	else if (pending & STATUSF_IP2) {
117		irq = txx9_irq();
118		if (irq == RBTX4938_IRQ_IOCINT)
119			irq = toshiba_rbtx4938_irq_nested(irq);
120	} else if (pending & STATUSF_IP1)
121		irq = MIPS_CPU_IRQ_BASE + 0;
122	else if (pending & STATUSF_IP0)
123		irq = MIPS_CPU_IRQ_BASE + 1;
124	else
125		irq = -1;
126	return irq;
127}
128
129static void __init toshiba_rbtx4938_irq_ioc_init(void)
130{
131	int i;
132
133	for (i = RBTX4938_IRQ_IOC;
134	     i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++)
135		irq_set_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
136					 handle_level_irq);
137
138	irq_set_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
139}
140
141void __init rbtx4938_irq_setup(void)
142{
143	txx9_irq_dispatch = rbtx4938_irq_dispatch;
144	/* Now, interrupt control disabled, */
145	/* all IRC interrupts are masked, */
146	/* all IRC interrupt mode are Low Active. */
147
148	/* mask all IOC interrupts */
149	writeb(0, rbtx4938_imask_addr);
150
151	/* clear SoftInt interrupts */
152	writeb(0, rbtx4938_softint_addr);
153	tx4938_irq_init();
154	toshiba_rbtx4938_irq_ioc_init();
155	/* Onboard 10M Ether: High Active */
156	irq_set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
157}
158