1/* 2 * TX4939 setup routines 3 * Based on linux/arch/mips/txx9/generic/setup_tx4938.c, 4 * and RBTX49xx patch from CELF patch archive. 5 * 6 * 2003-2005 (c) MontaVista Software, Inc. 7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file "COPYING" in the main directory of this archive 11 * for more details. 12 */ 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/delay.h> 16#include <linux/netdevice.h> 17#include <linux/notifier.h> 18#include <linux/device.h> 19#include <linux/ethtool.h> 20#include <linux/param.h> 21#include <linux/ptrace.h> 22#include <linux/mtd/physmap.h> 23#include <linux/platform_device.h> 24#include <asm/bootinfo.h> 25#include <asm/reboot.h> 26#include <asm/traps.h> 27#include <asm/txx9irq.h> 28#include <asm/txx9tmr.h> 29#include <asm/txx9/generic.h> 30#include <asm/txx9/ndfmc.h> 31#include <asm/txx9/dmac.h> 32#include <asm/txx9/tx4939.h> 33 34static void __init tx4939_wdr_init(void) 35{ 36 /* report watchdog reset status */ 37 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST) 38 pr_warn("Watchdog reset detected at 0x%lx\n", 39 read_c0_errorepc()); 40 /* clear WatchDogReset (W1C) */ 41 tx4939_ccfg_set(TX4939_CCFG_WDRST); 42 /* do reset on watchdog */ 43 tx4939_ccfg_set(TX4939_CCFG_WR); 44} 45 46void __init tx4939_wdt_init(void) 47{ 48 txx9_wdt_init(TX4939_TMR_REG(2) & 0xfffffffffULL); 49} 50 51static void tx4939_machine_restart(char *command) 52{ 53 local_irq_disable(); 54 pr_emerg("Rebooting (with %s watchdog reset)...\n", 55 (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) ? 56 "external" : "internal"); 57 /* clear watchdog status */ 58 tx4939_ccfg_set(TX4939_CCFG_WDRST); /* W1C */ 59 txx9_wdt_now(TX4939_TMR_REG(2) & 0xfffffffffULL); 60 while (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST)) 61 ; 62 mdelay(10); 63 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) { 64 pr_emerg("Rebooting (with internal watchdog reset)...\n"); 65 /* External WDRST failed. Do internal watchdog reset */ 66 tx4939_ccfg_clear(TX4939_CCFG_WDREXEN); 67 } 68 /* fallback */ 69 (*_machine_halt)(); 70} 71 72void show_registers(struct pt_regs *regs); 73static int tx4939_be_handler(struct pt_regs *regs, int is_fixup) 74{ 75 int data = regs->cp0_cause & 4; 76 console_verbose(); 77 pr_err("%cBE exception at %#lx\n", 78 data ? 'D' : 'I', regs->cp0_epc); 79 pr_err("ccfg:%llx, toea:%llx\n", 80 (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg), 81 (unsigned long long)____raw_readq(&tx4939_ccfgptr->toea)); 82#ifdef CONFIG_PCI 83 tx4927_report_pcic_status(); 84#endif 85 show_registers(regs); 86 panic("BusError!"); 87} 88static void __init tx4939_be_init(void) 89{ 90 board_be_handler = tx4939_be_handler; 91} 92 93static struct resource tx4939_sdram_resource[4]; 94static struct resource tx4939_sram_resource; 95#define TX4939_SRAM_SIZE 0x800 96 97void __init tx4939_add_memory_regions(void) 98{ 99 int i; 100 unsigned long start, size; 101 u64 win; 102 103 for (i = 0; i < 4; i++) { 104 if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i))) 105 continue; 106 win = ____raw_readq(&tx4939_ddrcptr->win[i]); 107 start = (unsigned long)(win >> 48); 108 size = (((unsigned long)(win >> 32) & 0xffff) + 1) - start; 109 add_memory_region(start << 20, size << 20, BOOT_MEM_RAM); 110 } 111} 112 113void __init tx4939_setup(void) 114{ 115 int i; 116 __u32 divmode; 117 __u64 pcfg; 118 unsigned int cpuclk = 0; 119 120 txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE, 121 TX4939_REG_SIZE); 122 set_c0_config(TX49_CONF_CWFON); 123 124 /* SDRAMC,EBUSC are configured by PROM */ 125 for (i = 0; i < 4; i++) { 126 if (!(TX4939_EBUSC_CR(i) & 0x8)) 127 continue; /* disabled */ 128 txx9_ce_res[i].start = (unsigned long)TX4939_EBUSC_BA(i); 129 txx9_ce_res[i].end = 130 txx9_ce_res[i].start + TX4939_EBUSC_SIZE(i) - 1; 131 request_resource(&iomem_resource, &txx9_ce_res[i]); 132 } 133 134 /* clocks */ 135 if (txx9_master_clock) { 136 /* calculate cpu_clock from master_clock */ 137 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) & 138 TX4939_CCFG_MULCLK_MASK; 139 cpuclk = txx9_master_clock * 20 / 2; 140 switch (divmode) { 141 case TX4939_CCFG_MULCLK_8: 142 cpuclk = cpuclk / 3 * 4 /* / 6 * 8 */; break; 143 case TX4939_CCFG_MULCLK_9: 144 cpuclk = cpuclk / 2 * 3 /* / 6 * 9 */; break; 145 case TX4939_CCFG_MULCLK_10: 146 cpuclk = cpuclk / 3 * 5 /* / 6 * 10 */; break; 147 case TX4939_CCFG_MULCLK_11: 148 cpuclk = cpuclk / 6 * 11; break; 149 case TX4939_CCFG_MULCLK_12: 150 cpuclk = cpuclk * 2 /* / 6 * 12 */; break; 151 case TX4939_CCFG_MULCLK_13: 152 cpuclk = cpuclk / 6 * 13; break; 153 case TX4939_CCFG_MULCLK_14: 154 cpuclk = cpuclk / 3 * 7 /* / 6 * 14 */; break; 155 case TX4939_CCFG_MULCLK_15: 156 cpuclk = cpuclk / 2 * 5 /* / 6 * 15 */; break; 157 } 158 txx9_cpu_clock = cpuclk; 159 } else { 160 if (txx9_cpu_clock == 0) 161 txx9_cpu_clock = 400000000; /* 400MHz */ 162 /* calculate master_clock from cpu_clock */ 163 cpuclk = txx9_cpu_clock; 164 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) & 165 TX4939_CCFG_MULCLK_MASK; 166 switch (divmode) { 167 case TX4939_CCFG_MULCLK_8: 168 txx9_master_clock = cpuclk * 6 / 8; break; 169 case TX4939_CCFG_MULCLK_9: 170 txx9_master_clock = cpuclk * 6 / 9; break; 171 case TX4939_CCFG_MULCLK_10: 172 txx9_master_clock = cpuclk * 6 / 10; break; 173 case TX4939_CCFG_MULCLK_11: 174 txx9_master_clock = cpuclk * 6 / 11; break; 175 case TX4939_CCFG_MULCLK_12: 176 txx9_master_clock = cpuclk * 6 / 12; break; 177 case TX4939_CCFG_MULCLK_13: 178 txx9_master_clock = cpuclk * 6 / 13; break; 179 case TX4939_CCFG_MULCLK_14: 180 txx9_master_clock = cpuclk * 6 / 14; break; 181 case TX4939_CCFG_MULCLK_15: 182 txx9_master_clock = cpuclk * 6 / 15; break; 183 } 184 txx9_master_clock /= 10; /* * 2 / 20 */ 185 } 186 /* calculate gbus_clock from cpu_clock */ 187 divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) & 188 TX4939_CCFG_YDIVMODE_MASK; 189 txx9_gbus_clock = txx9_cpu_clock; 190 switch (divmode) { 191 case TX4939_CCFG_YDIVMODE_2: 192 txx9_gbus_clock /= 2; break; 193 case TX4939_CCFG_YDIVMODE_3: 194 txx9_gbus_clock /= 3; break; 195 case TX4939_CCFG_YDIVMODE_5: 196 txx9_gbus_clock /= 5; break; 197 case TX4939_CCFG_YDIVMODE_6: 198 txx9_gbus_clock /= 6; break; 199 } 200 /* change default value to udelay/mdelay take reasonable time */ 201 loops_per_jiffy = txx9_cpu_clock / HZ / 2; 202 203 /* CCFG */ 204 tx4939_wdr_init(); 205 /* clear BusErrorOnWrite flag (W1C) */ 206 tx4939_ccfg_set(TX4939_CCFG_WDRST | TX4939_CCFG_BEOW); 207 /* enable Timeout BusError */ 208 if (txx9_ccfg_toeon) 209 tx4939_ccfg_set(TX4939_CCFG_TOE); 210 211 /* DMA selection */ 212 txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_DMASEL_ALL); 213 214 /* Use external clock for external arbiter */ 215 if (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB)) 216 txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_PCICLKEN_ALL); 217 218 pr_info("%s -- %dMHz(M%dMHz,G%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n", 219 txx9_pcode_str, 220 (cpuclk + 500000) / 1000000, 221 (txx9_master_clock + 500000) / 1000000, 222 (txx9_gbus_clock + 500000) / 1000000, 223 (__u32)____raw_readq(&tx4939_ccfgptr->crir), 224 (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg), 225 (unsigned long long)____raw_readq(&tx4939_ccfgptr->pcfg)); 226 227 pr_info("%s DDRC -- EN:%08x", txx9_pcode_str, 228 (__u32)____raw_readq(&tx4939_ddrcptr->winen)); 229 for (i = 0; i < 4; i++) { 230 __u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]); 231 if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i))) 232 continue; /* disabled */ 233 printk(KERN_CONT " #%d:%016llx", i, (unsigned long long)win); 234 tx4939_sdram_resource[i].name = "DDR SDRAM"; 235 tx4939_sdram_resource[i].start = 236 (unsigned long)(win >> 48) << 20; 237 tx4939_sdram_resource[i].end = 238 ((((unsigned long)(win >> 32) & 0xffff) + 1) << 239 20) - 1; 240 tx4939_sdram_resource[i].flags = IORESOURCE_MEM; 241 request_resource(&iomem_resource, &tx4939_sdram_resource[i]); 242 } 243 printk(KERN_CONT "\n"); 244 245 /* SRAM */ 246 if (____raw_readq(&tx4939_sramcptr->cr) & 1) { 247 unsigned int size = TX4939_SRAM_SIZE; 248 tx4939_sram_resource.name = "SRAM"; 249 tx4939_sram_resource.start = 250 (____raw_readq(&tx4939_sramcptr->cr) >> (39-11)) 251 & ~(size - 1); 252 tx4939_sram_resource.end = 253 tx4939_sram_resource.start + TX4939_SRAM_SIZE - 1; 254 tx4939_sram_resource.flags = IORESOURCE_MEM; 255 request_resource(&iomem_resource, &tx4939_sram_resource); 256 } 257 258 /* TMR */ 259 /* disable all timers */ 260 for (i = 0; i < TX4939_NR_TMR; i++) 261 txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL); 262 263 /* set PCIC1 reset (required to prevent hangup on BIST) */ 264 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST); 265 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg); 266 if (pcfg & (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE)) { 267 mdelay(1); /* at least 128 cpu clock */ 268 /* clear PCIC1 reset */ 269 txx9_clear64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST); 270 } else { 271 pr_info("%s: stop PCIC1\n", txx9_pcode_str); 272 /* stop PCIC1 */ 273 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1CKD); 274 } 275 if (!(pcfg & TX4939_PCFG_ET0MODE)) { 276 pr_info("%s: stop ETH0\n", txx9_pcode_str); 277 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0RST); 278 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0CKD); 279 } 280 if (!(pcfg & TX4939_PCFG_ET1MODE)) { 281 pr_info("%s: stop ETH1\n", txx9_pcode_str); 282 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1RST); 283 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1CKD); 284 } 285 286 _machine_restart = tx4939_machine_restart; 287 board_be_init = tx4939_be_init; 288} 289 290void __init tx4939_time_init(unsigned int tmrnr) 291{ 292 if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_TINTDIS) 293 txx9_clockevent_init(TX4939_TMR_REG(tmrnr) & 0xfffffffffULL, 294 TXX9_IRQ_BASE + TX4939_IR_TMR(tmrnr), 295 TXX9_IMCLK); 296} 297 298void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask) 299{ 300 int i; 301 unsigned int ch_mask = 0; 302 __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg); 303 304 cts_mask |= ~1; /* only SIO0 have RTS/CTS */ 305 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO0) 306 cts_mask |= 1 << 0; /* disable SIO0 RTS/CTS by PCFG setting */ 307 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2) 308 ch_mask |= 1 << 2; /* disable SIO2 by PCFG setting */ 309 if (pcfg & TX4939_PCFG_SIO3MODE) 310 ch_mask |= 1 << 3; /* disable SIO3 by PCFG setting */ 311 for (i = 0; i < 4; i++) { 312 if ((1 << i) & ch_mask) 313 continue; 314 txx9_sio_init(TX4939_SIO_REG(i) & 0xfffffffffULL, 315 TXX9_IRQ_BASE + TX4939_IR_SIO(i), 316 i, sclk, (1 << i) & cts_mask); 317 } 318} 319 320#if IS_ENABLED(CONFIG_TC35815) 321static u32 tx4939_get_eth_speed(struct net_device *dev) 322{ 323 struct ethtool_cmd cmd; 324 if (__ethtool_get_settings(dev, &cmd)) 325 return 100; /* default 100Mbps */ 326 327 return ethtool_cmd_speed(&cmd); 328} 329 330static int tx4939_netdev_event(struct notifier_block *this, 331 unsigned long event, 332 void *ptr) 333{ 334 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 335 336 if (event == NETDEV_CHANGE && netif_carrier_ok(dev)) { 337 __u64 bit = 0; 338 if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(0)) 339 bit = TX4939_PCFG_SPEED0; 340 else if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(1)) 341 bit = TX4939_PCFG_SPEED1; 342 if (bit) { 343 if (tx4939_get_eth_speed(dev) == 100) 344 txx9_set64(&tx4939_ccfgptr->pcfg, bit); 345 else 346 txx9_clear64(&tx4939_ccfgptr->pcfg, bit); 347 } 348 } 349 return NOTIFY_DONE; 350} 351 352static struct notifier_block tx4939_netdev_notifier = { 353 .notifier_call = tx4939_netdev_event, 354 .priority = 1, 355}; 356 357void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1) 358{ 359 u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg); 360 361 if (addr0 && (pcfg & TX4939_PCFG_ET0MODE)) 362 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(0), addr0); 363 if (addr1 && (pcfg & TX4939_PCFG_ET1MODE)) 364 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(1), addr1); 365 register_netdevice_notifier(&tx4939_netdev_notifier); 366} 367#else 368void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1) 369{ 370} 371#endif 372 373void __init tx4939_mtd_init(int ch) 374{ 375 struct physmap_flash_data pdata = { 376 .width = TX4939_EBUSC_WIDTH(ch) / 8, 377 }; 378 unsigned long start = txx9_ce_res[ch].start; 379 unsigned long size = txx9_ce_res[ch].end - start + 1; 380 381 if (!(TX4939_EBUSC_CR(ch) & 0x8)) 382 return; /* disabled */ 383 txx9_physmap_flash_init(ch, start, size, &pdata); 384} 385 386#define TX4939_ATA_REG_PHYS(ch) (TX4939_ATA_REG(ch) & 0xfffffffffULL) 387void __init tx4939_ata_init(void) 388{ 389 static struct resource ata0_res[] = { 390 { 391 .start = TX4939_ATA_REG_PHYS(0), 392 .end = TX4939_ATA_REG_PHYS(0) + 0x1000 - 1, 393 .flags = IORESOURCE_MEM, 394 }, { 395 .start = TXX9_IRQ_BASE + TX4939_IR_ATA(0), 396 .flags = IORESOURCE_IRQ, 397 }, 398 }; 399 static struct resource ata1_res[] = { 400 { 401 .start = TX4939_ATA_REG_PHYS(1), 402 .end = TX4939_ATA_REG_PHYS(1) + 0x1000 - 1, 403 .flags = IORESOURCE_MEM, 404 }, { 405 .start = TXX9_IRQ_BASE + TX4939_IR_ATA(1), 406 .flags = IORESOURCE_IRQ, 407 }, 408 }; 409 static struct platform_device ata0_dev = { 410 .name = "tx4939ide", 411 .id = 0, 412 .num_resources = ARRAY_SIZE(ata0_res), 413 .resource = ata0_res, 414 }; 415 static struct platform_device ata1_dev = { 416 .name = "tx4939ide", 417 .id = 1, 418 .num_resources = ARRAY_SIZE(ata1_res), 419 .resource = ata1_res, 420 }; 421 __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg); 422 423 if (pcfg & TX4939_PCFG_ATA0MODE) 424 platform_device_register(&ata0_dev); 425 if ((pcfg & (TX4939_PCFG_ATA1MODE | 426 TX4939_PCFG_ET1MODE | 427 TX4939_PCFG_ET0MODE)) == TX4939_PCFG_ATA1MODE) 428 platform_device_register(&ata1_dev); 429} 430 431void __init tx4939_rtc_init(void) 432{ 433 static struct resource res[] = { 434 { 435 .start = TX4939_RTC_REG & 0xfffffffffULL, 436 .end = (TX4939_RTC_REG & 0xfffffffffULL) + 0x100 - 1, 437 .flags = IORESOURCE_MEM, 438 }, { 439 .start = TXX9_IRQ_BASE + TX4939_IR_RTC, 440 .flags = IORESOURCE_IRQ, 441 }, 442 }; 443 static struct platform_device rtc_dev = { 444 .name = "tx4939rtc", 445 .id = -1, 446 .num_resources = ARRAY_SIZE(res), 447 .resource = res, 448 }; 449 450 platform_device_register(&rtc_dev); 451} 452 453void __init tx4939_ndfmc_init(unsigned int hold, unsigned int spw, 454 unsigned char ch_mask, unsigned char wide_mask) 455{ 456 struct txx9ndfmc_platform_data plat_data = { 457 .shift = 1, 458 .gbus_clock = txx9_gbus_clock, 459 .hold = hold, 460 .spw = spw, 461 .flags = NDFMC_PLAT_FLAG_NO_RSTR | NDFMC_PLAT_FLAG_HOLDADD | 462 NDFMC_PLAT_FLAG_DUMMYWRITE, 463 .ch_mask = ch_mask, 464 .wide_mask = wide_mask, 465 }; 466 txx9_ndfmc_init(TX4939_NDFMC_REG & 0xfffffffffULL, &plat_data); 467} 468 469void __init tx4939_dmac_init(int memcpy_chan0, int memcpy_chan1) 470{ 471 struct txx9dmac_platform_data plat_data = { 472 .have_64bit_regs = true, 473 }; 474 int i; 475 476 for (i = 0; i < 2; i++) { 477 plat_data.memcpy_chan = i ? memcpy_chan1 : memcpy_chan0; 478 txx9_dmac_init(i, TX4939_DMA_REG(i) & 0xfffffffffULL, 479 TXX9_IRQ_BASE + TX4939_IR_DMA(i, 0), 480 &plat_data); 481 } 482} 483 484void __init tx4939_aclc_init(void) 485{ 486 u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg); 487 488 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_ACLC) 489 txx9_aclc_init(TX4939_ACLC_REG & 0xfffffffffULL, 490 TXX9_IRQ_BASE + TX4939_IR_ACLC, 1, 0, 1); 491} 492 493void __init tx4939_sramc_init(void) 494{ 495 if (tx4939_sram_resource.start) 496 txx9_sramc_init(&tx4939_sram_resource); 497} 498 499void __init tx4939_rng_init(void) 500{ 501 static struct resource res = { 502 .start = TX4939_RNG_REG & 0xfffffffffULL, 503 .end = (TX4939_RNG_REG & 0xfffffffffULL) + 0x30 - 1, 504 .flags = IORESOURCE_MEM, 505 }; 506 static struct platform_device pdev = { 507 .name = "tx4939-rng", 508 .id = -1, 509 .num_resources = 1, 510 .resource = &res, 511 }; 512 513 platform_device_register(&pdev); 514} 515 516static void __init tx4939_stop_unused_modules(void) 517{ 518 __u64 pcfg, rst = 0, ckd = 0; 519 char buf[128]; 520 521 buf[0] = '\0'; 522 local_irq_disable(); 523 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg); 524 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) != 525 TX4939_PCFG_I2SMODE_ACLC) { 526 rst |= TX4939_CLKCTR_ACLRST; 527 ckd |= TX4939_CLKCTR_ACLCKD; 528 strcat(buf, " ACLC"); 529 } 530 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) != 531 TX4939_PCFG_I2SMODE_I2S && 532 (pcfg & TX4939_PCFG_I2SMODE_MASK) != 533 TX4939_PCFG_I2SMODE_I2S_ALT) { 534 rst |= TX4939_CLKCTR_I2SRST; 535 ckd |= TX4939_CLKCTR_I2SCKD; 536 strcat(buf, " I2S"); 537 } 538 if (!(pcfg & TX4939_PCFG_ATA0MODE)) { 539 rst |= TX4939_CLKCTR_ATA0RST; 540 ckd |= TX4939_CLKCTR_ATA0CKD; 541 strcat(buf, " ATA0"); 542 } 543 if (!(pcfg & TX4939_PCFG_ATA1MODE)) { 544 rst |= TX4939_CLKCTR_ATA1RST; 545 ckd |= TX4939_CLKCTR_ATA1CKD; 546 strcat(buf, " ATA1"); 547 } 548 if (pcfg & TX4939_PCFG_SPIMODE) { 549 rst |= TX4939_CLKCTR_SPIRST; 550 ckd |= TX4939_CLKCTR_SPICKD; 551 strcat(buf, " SPI"); 552 } 553 if (!(pcfg & (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE))) { 554 rst |= TX4939_CLKCTR_VPCRST; 555 ckd |= TX4939_CLKCTR_VPCCKD; 556 strcat(buf, " VPC"); 557 } 558 if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2) { 559 rst |= TX4939_CLKCTR_SIO2RST; 560 ckd |= TX4939_CLKCTR_SIO2CKD; 561 strcat(buf, " SIO2"); 562 } 563 if (pcfg & TX4939_PCFG_SIO3MODE) { 564 rst |= TX4939_CLKCTR_SIO3RST; 565 ckd |= TX4939_CLKCTR_SIO3CKD; 566 strcat(buf, " SIO3"); 567 } 568 if (rst | ckd) { 569 txx9_set64(&tx4939_ccfgptr->clkctr, rst); 570 txx9_set64(&tx4939_ccfgptr->clkctr, ckd); 571 } 572 local_irq_enable(); 573 if (buf[0]) 574 pr_info("%s: stop%s\n", txx9_pcode_str, buf); 575} 576 577static int __init tx4939_late_init(void) 578{ 579 if (txx9_pcode != 0x4939) 580 return -ENODEV; 581 tx4939_stop_unused_modules(); 582 return 0; 583} 584late_initcall(tx4939_late_init); 585