1/*
2 * Copyright (C) 2001,2002,2004 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
17 */
18
19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/smp.h>
22#include <linux/kernel_stat.h>
23#include <linux/sched.h>
24
25#include <asm/mmu_context.h>
26#include <asm/io.h>
27#include <asm/fw/cfe/cfe_api.h>
28#include <asm/sibyte/sb1250.h>
29#include <asm/sibyte/bcm1480_regs.h>
30#include <asm/sibyte/bcm1480_int.h>
31
32extern void smp_call_function_interrupt(void);
33
34/*
35 * These are routines for dealing with the bcm1480 smp capabilities
36 * independent of board/firmware
37 */
38
39static void *mailbox_0_set_regs[] = {
40	IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
41	IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
42	IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
43	IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
44};
45
46static void *mailbox_0_clear_regs[] = {
47	IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
48	IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
49	IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
50	IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
51};
52
53static void *mailbox_0_regs[] = {
54	IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
55	IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
56	IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
57	IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
58};
59
60/*
61 * SMP init and finish on secondary CPUs
62 */
63void bcm1480_smp_init(void)
64{
65	unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
66		STATUSF_IP1 | STATUSF_IP0;
67
68	/* Set interrupt mask, but don't enable */
69	change_c0_status(ST0_IM, imask);
70}
71
72/*
73 * These are routines for dealing with the sb1250 smp capabilities
74 * independent of board/firmware
75 */
76
77/*
78 * Simple enough; everything is set up, so just poke the appropriate mailbox
79 * register, and we should be set
80 */
81static void bcm1480_send_ipi_single(int cpu, unsigned int action)
82{
83	__raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]);
84}
85
86static void bcm1480_send_ipi_mask(const struct cpumask *mask,
87				  unsigned int action)
88{
89	unsigned int i;
90
91	for_each_cpu(i, mask)
92		bcm1480_send_ipi_single(i, action);
93}
94
95/*
96 * Code to run on secondary just after probing the CPU
97 */
98static void bcm1480_init_secondary(void)
99{
100	extern void bcm1480_smp_init(void);
101
102	bcm1480_smp_init();
103}
104
105/*
106 * Do any tidying up before marking online and running the idle
107 * loop
108 */
109static void bcm1480_smp_finish(void)
110{
111	extern void sb1480_clockevent_init(void);
112
113	sb1480_clockevent_init();
114	local_irq_enable();
115}
116
117/*
118 * Setup the PC, SP, and GP of a secondary processor and start it
119 * running!
120 */
121static void bcm1480_boot_secondary(int cpu, struct task_struct *idle)
122{
123	int retval;
124
125	retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap,
126			       __KSTK_TOS(idle),
127			       (unsigned long)task_thread_info(idle), 0);
128	if (retval != 0)
129		printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval);
130}
131
132/*
133 * Use CFE to find out how many CPUs are available, setting up
134 * cpu_possible_mask and the logical/physical mappings.
135 * XXXKW will the boot CPU ever not be physical 0?
136 *
137 * Common setup before any secondaries are started
138 */
139static void __init bcm1480_smp_setup(void)
140{
141	int i, num;
142
143	init_cpu_possible(cpumask_of(0));
144	__cpu_number_map[0] = 0;
145	__cpu_logical_map[0] = 0;
146
147	for (i = 1, num = 0; i < NR_CPUS; i++) {
148		if (cfe_cpu_stop(i) == 0) {
149			set_cpu_possible(i, true);
150			__cpu_number_map[i] = ++num;
151			__cpu_logical_map[num] = i;
152		}
153	}
154	printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
155}
156
157static void __init bcm1480_prepare_cpus(unsigned int max_cpus)
158{
159}
160
161struct plat_smp_ops bcm1480_smp_ops = {
162	.send_ipi_single	= bcm1480_send_ipi_single,
163	.send_ipi_mask		= bcm1480_send_ipi_mask,
164	.init_secondary		= bcm1480_init_secondary,
165	.smp_finish		= bcm1480_smp_finish,
166	.boot_secondary		= bcm1480_boot_secondary,
167	.smp_setup		= bcm1480_smp_setup,
168	.prepare_cpus		= bcm1480_prepare_cpus,
169};
170
171void bcm1480_mailbox_interrupt(void)
172{
173	int cpu = smp_processor_id();
174	int irq = K_BCM1480_INT_MBOX_0_0;
175	unsigned int action;
176
177	kstat_incr_irq_this_cpu(irq);
178	/* Load the mailbox register to figure out what we're supposed to do */
179	action = (__raw_readq(mailbox_0_regs[cpu]) >> 48) & 0xffff;
180
181	/* Clear the mailbox to clear the interrupt */
182	__raw_writeq(((u64)action)<<48, mailbox_0_clear_regs[cpu]);
183
184	if (action & SMP_RESCHEDULE_YOURSELF)
185		scheduler_ipi();
186
187	if (action & SMP_CALL_FUNCTION)
188		smp_call_function_interrupt();
189}
190