1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
8 */
9
10#include <linux/io.h>
11#include <linux/bitops.h>
12#include <linux/of_platform.h>
13#include <linux/of_address.h>
14#include <linux/of_irq.h>
15#include <linux/irqdomain.h>
16#include <linux/interrupt.h>
17
18#include <asm/irq_cpu.h>
19#include <asm/mipsregs.h>
20
21#include "common.h"
22
23#define INTC_INT_GLOBAL		BIT(31)
24
25#define RALINK_CPU_IRQ_INTC	(MIPS_CPU_IRQ_BASE + 2)
26#define RALINK_CPU_IRQ_PCI	(MIPS_CPU_IRQ_BASE + 4)
27#define RALINK_CPU_IRQ_FE	(MIPS_CPU_IRQ_BASE + 5)
28#define RALINK_CPU_IRQ_WIFI	(MIPS_CPU_IRQ_BASE + 6)
29#define RALINK_CPU_IRQ_COUNTER	(MIPS_CPU_IRQ_BASE + 7)
30
31/* we have a cascade of 8 irqs */
32#define RALINK_INTC_IRQ_BASE	8
33
34/* we have 32 SoC irqs */
35#define RALINK_INTC_IRQ_COUNT	32
36
37#define RALINK_INTC_IRQ_PERFC   (RALINK_INTC_IRQ_BASE + 9)
38
39enum rt_intc_regs_enum {
40	INTC_REG_STATUS0 = 0,
41	INTC_REG_STATUS1,
42	INTC_REG_TYPE,
43	INTC_REG_RAW_STATUS,
44	INTC_REG_ENABLE,
45	INTC_REG_DISABLE,
46};
47
48static u32 rt_intc_regs[] = {
49	[INTC_REG_STATUS0] = 0x00,
50	[INTC_REG_STATUS1] = 0x04,
51	[INTC_REG_TYPE] = 0x20,
52	[INTC_REG_RAW_STATUS] = 0x30,
53	[INTC_REG_ENABLE] = 0x34,
54	[INTC_REG_DISABLE] = 0x38,
55};
56
57static void __iomem *rt_intc_membase;
58
59static int rt_perfcount_irq;
60
61static inline void rt_intc_w32(u32 val, unsigned reg)
62{
63	__raw_writel(val, rt_intc_membase + rt_intc_regs[reg]);
64}
65
66static inline u32 rt_intc_r32(unsigned reg)
67{
68	return __raw_readl(rt_intc_membase + rt_intc_regs[reg]);
69}
70
71static void ralink_intc_irq_unmask(struct irq_data *d)
72{
73	rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE);
74}
75
76static void ralink_intc_irq_mask(struct irq_data *d)
77{
78	rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE);
79}
80
81static struct irq_chip ralink_intc_irq_chip = {
82	.name		= "INTC",
83	.irq_unmask	= ralink_intc_irq_unmask,
84	.irq_mask	= ralink_intc_irq_mask,
85	.irq_mask_ack	= ralink_intc_irq_mask,
86};
87
88int get_c0_perfcount_int(void)
89{
90	return rt_perfcount_irq;
91}
92EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
93
94unsigned int get_c0_compare_int(void)
95{
96	return CP0_LEGACY_COMPARE_IRQ;
97}
98
99static void ralink_intc_irq_handler(unsigned int irq, struct irq_desc *desc)
100{
101	u32 pending = rt_intc_r32(INTC_REG_STATUS0);
102
103	if (pending) {
104		struct irq_domain *domain = irq_get_handler_data(irq);
105		generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
106	} else {
107		spurious_interrupt();
108	}
109}
110
111asmlinkage void plat_irq_dispatch(void)
112{
113	unsigned long pending;
114
115	pending = read_c0_status() & read_c0_cause() & ST0_IM;
116
117	if (pending & STATUSF_IP7)
118		do_IRQ(RALINK_CPU_IRQ_COUNTER);
119
120	else if (pending & STATUSF_IP5)
121		do_IRQ(RALINK_CPU_IRQ_FE);
122
123	else if (pending & STATUSF_IP6)
124		do_IRQ(RALINK_CPU_IRQ_WIFI);
125
126	else if (pending & STATUSF_IP4)
127		do_IRQ(RALINK_CPU_IRQ_PCI);
128
129	else if (pending & STATUSF_IP2)
130		do_IRQ(RALINK_CPU_IRQ_INTC);
131
132	else
133		spurious_interrupt();
134}
135
136static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
137{
138	irq_set_chip_and_handler(irq, &ralink_intc_irq_chip, handle_level_irq);
139
140	return 0;
141}
142
143static const struct irq_domain_ops irq_domain_ops = {
144	.xlate = irq_domain_xlate_onecell,
145	.map = intc_map,
146};
147
148static int __init intc_of_init(struct device_node *node,
149			       struct device_node *parent)
150{
151	struct resource res;
152	struct irq_domain *domain;
153	int irq;
154
155	if (!of_property_read_u32_array(node, "ralink,intc-registers",
156					rt_intc_regs, 6))
157		pr_info("intc: using register map from devicetree\n");
158
159	irq = irq_of_parse_and_map(node, 0);
160	if (!irq)
161		panic("Failed to get INTC IRQ");
162
163	if (of_address_to_resource(node, 0, &res))
164		panic("Failed to get intc memory range");
165
166	if (request_mem_region(res.start, resource_size(&res),
167				res.name) < 0)
168		pr_err("Failed to request intc memory");
169
170	rt_intc_membase = ioremap_nocache(res.start,
171					resource_size(&res));
172	if (!rt_intc_membase)
173		panic("Failed to remap intc memory");
174
175	/* disable all interrupts */
176	rt_intc_w32(~0, INTC_REG_DISABLE);
177
178	/* route all INTC interrupts to MIPS HW0 interrupt */
179	rt_intc_w32(0, INTC_REG_TYPE);
180
181	domain = irq_domain_add_legacy(node, RALINK_INTC_IRQ_COUNT,
182			RALINK_INTC_IRQ_BASE, 0, &irq_domain_ops, NULL);
183	if (!domain)
184		panic("Failed to add irqdomain");
185
186	rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE);
187
188	irq_set_chained_handler(irq, ralink_intc_irq_handler);
189	irq_set_handler_data(irq, domain);
190
191	/* tell the kernel which irq is used for performance monitoring */
192	rt_perfcount_irq = irq_create_mapping(domain, 9);
193
194	return 0;
195}
196
197static struct of_device_id __initdata of_irq_ids[] = {
198	{ .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
199	{ .compatible = "ralink,rt2880-intc", .data = intc_of_init },
200	{},
201};
202
203void __init arch_init_irq(void)
204{
205	of_irq_init(of_irq_ids);
206}
207
208