1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses.  You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 *    notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 *    notice, this list of conditions and the following disclaimer in
19 *    the documentation and/or other materials provided with the
20 *    distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/delay.h>
37#include <linux/init.h>
38#include <linux/smp.h>
39#include <linux/irq.h>
40
41#include <asm/mmu_context.h>
42
43#include <asm/netlogic/interrupt.h>
44#include <asm/netlogic/mips-extns.h>
45#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
47
48#if defined(CONFIG_CPU_XLP)
49#include <asm/netlogic/xlp-hal/iomap.h>
50#include <asm/netlogic/xlp-hal/xlp.h>
51#include <asm/netlogic/xlp-hal/pic.h>
52#elif defined(CONFIG_CPU_XLR)
53#include <asm/netlogic/xlr/iomap.h>
54#include <asm/netlogic/xlr/pic.h>
55#include <asm/netlogic/xlr/xlr.h>
56#else
57#error "Unknown CPU"
58#endif
59
60void nlm_send_ipi_single(int logical_cpu, unsigned int action)
61{
62	unsigned int hwtid;
63	uint64_t picbase;
64
65	/* node id is part of hwtid, and needed for send_ipi */
66	hwtid = cpu_logical_map(logical_cpu);
67	picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase;
68
69	if (action & SMP_CALL_FUNCTION)
70		nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_FUNCTION, 0);
71	if (action & SMP_RESCHEDULE_YOURSELF)
72		nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_RESCHEDULE, 0);
73}
74
75void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
76{
77	int cpu;
78
79	for_each_cpu(cpu, mask) {
80		nlm_send_ipi_single(cpu, action);
81	}
82}
83
84/* IRQ_IPI_SMP_FUNCTION Handler */
85void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc)
86{
87	clear_c0_eimr(irq);
88	ack_c0_eirr(irq);
89	smp_call_function_interrupt();
90	set_c0_eimr(irq);
91}
92
93/* IRQ_IPI_SMP_RESCHEDULE  handler */
94void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc)
95{
96	clear_c0_eimr(irq);
97	ack_c0_eirr(irq);
98	scheduler_ipi();
99	set_c0_eimr(irq);
100}
101
102/*
103 * Called before going into mips code, early cpu init
104 */
105void nlm_early_init_secondary(int cpu)
106{
107	change_c0_config(CONF_CM_CMASK, 0x3);
108#ifdef CONFIG_CPU_XLP
109	xlp_mmu_init();
110#endif
111	write_c0_ebase(nlm_current_node()->ebase);
112}
113
114/*
115 * Code to run on secondary just after probing the CPU
116 */
117static void nlm_init_secondary(void)
118{
119	int hwtid;
120
121	hwtid = hard_smp_processor_id();
122	current_cpu_data.core = hwtid / NLM_THREADS_PER_CORE;
123	current_cpu_data.package = nlm_nodeid();
124	nlm_percpu_init(hwtid);
125	nlm_smp_irq_init(hwtid);
126}
127
128void nlm_prepare_cpus(unsigned int max_cpus)
129{
130	/* declare we are SMT capable */
131	smp_num_siblings = nlm_threads_per_core;
132}
133
134void nlm_smp_finish(void)
135{
136	local_irq_enable();
137}
138
139/*
140 * Boot all other cpus in the system, initialize them, and bring them into
141 * the boot function
142 */
143unsigned long nlm_next_gp;
144unsigned long nlm_next_sp;
145static cpumask_t phys_cpu_present_mask;
146
147void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
148{
149	uint64_t picbase;
150	int hwtid;
151
152	hwtid = cpu_logical_map(logical_cpu);
153	picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase;
154
155	nlm_next_sp = (unsigned long)__KSTK_TOS(idle);
156	nlm_next_gp = (unsigned long)task_thread_info(idle);
157
158	/* barrier for sp/gp store above */
159	__sync();
160	nlm_pic_send_ipi(picbase, hwtid, 1, 1);  /* NMI */
161}
162
163void __init nlm_smp_setup(void)
164{
165	unsigned int boot_cpu;
166	int num_cpus, i, ncore, node;
167	volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
168
169	boot_cpu = hard_smp_processor_id();
170	cpumask_clear(&phys_cpu_present_mask);
171
172	cpumask_set_cpu(boot_cpu, &phys_cpu_present_mask);
173	__cpu_number_map[boot_cpu] = 0;
174	__cpu_logical_map[0] = boot_cpu;
175	set_cpu_possible(0, true);
176
177	num_cpus = 1;
178	for (i = 0; i < NR_CPUS; i++) {
179		/*
180		 * cpu_ready array is not set for the boot_cpu,
181		 * it is only set for ASPs (see smpboot.S)
182		 */
183		if (cpu_ready[i]) {
184			cpumask_set_cpu(i, &phys_cpu_present_mask);
185			__cpu_number_map[i] = num_cpus;
186			__cpu_logical_map[num_cpus] = i;
187			set_cpu_possible(num_cpus, true);
188			node = nlm_hwtid_to_node(i);
189			cpumask_set_cpu(num_cpus, &nlm_get_node(node)->cpumask);
190			++num_cpus;
191		}
192	}
193
194	pr_info("Physical CPU mask: %*pb\n",
195		cpumask_pr_args(&phys_cpu_present_mask));
196	pr_info("Possible CPU mask: %*pb\n",
197		cpumask_pr_args(cpu_possible_mask));
198
199	/* check with the cores we have woken up */
200	for (ncore = 0, i = 0; i < NLM_NR_NODES; i++)
201		ncore += hweight32(nlm_get_node(i)->coremask);
202
203	pr_info("Detected (%dc%dt) %d Slave CPU(s)\n", ncore,
204		nlm_threads_per_core, num_cpus);
205
206	/* switch NMI handler to boot CPUs */
207	nlm_set_nmi_handler(nlm_boot_secondary_cpus);
208}
209
210static int nlm_parse_cpumask(cpumask_t *wakeup_mask)
211{
212	uint32_t core0_thr_mask, core_thr_mask;
213	int threadmode, i, j;
214
215	core0_thr_mask = 0;
216	for (i = 0; i < NLM_THREADS_PER_CORE; i++)
217		if (cpumask_test_cpu(i, wakeup_mask))
218			core0_thr_mask |= (1 << i);
219	switch (core0_thr_mask) {
220	case 1:
221		nlm_threads_per_core = 1;
222		threadmode = 0;
223		break;
224	case 3:
225		nlm_threads_per_core = 2;
226		threadmode = 2;
227		break;
228	case 0xf:
229		nlm_threads_per_core = 4;
230		threadmode = 3;
231		break;
232	default:
233		goto unsupp;
234	}
235
236	/* Verify other cores CPU masks */
237	for (i = 0; i < NR_CPUS; i += NLM_THREADS_PER_CORE) {
238		core_thr_mask = 0;
239		for (j = 0; j < NLM_THREADS_PER_CORE; j++)
240			if (cpumask_test_cpu(i + j, wakeup_mask))
241				core_thr_mask |= (1 << j);
242		if (core_thr_mask != 0 && core_thr_mask != core0_thr_mask)
243				goto unsupp;
244	}
245	return threadmode;
246
247unsupp:
248	panic("Unsupported CPU mask %*pb", cpumask_pr_args(wakeup_mask));
249	return 0;
250}
251
252int nlm_wakeup_secondary_cpus(void)
253{
254	u32 *reset_data;
255	int threadmode;
256
257	/* verify the mask and setup core config variables */
258	threadmode = nlm_parse_cpumask(&nlm_cpumask);
259
260	/* Setup CPU init parameters */
261	reset_data = nlm_get_boot_data(BOOT_THREAD_MODE);
262	*reset_data = threadmode;
263
264#ifdef CONFIG_CPU_XLP
265	xlp_wakeup_secondary_cpus();
266#else
267	xlr_wakeup_secondary_cpus();
268#endif
269	return 0;
270}
271
272struct plat_smp_ops nlm_smp_ops = {
273	.send_ipi_single	= nlm_send_ipi_single,
274	.send_ipi_mask		= nlm_send_ipi_mask,
275	.init_secondary		= nlm_init_secondary,
276	.smp_finish		= nlm_smp_finish,
277	.boot_secondary		= nlm_boot_secondary,
278	.smp_setup		= nlm_smp_setup,
279	.prepare_cpus		= nlm_prepare_cpus,
280};
281