1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License.  See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Carsten Langgaard, carstenl@mips.com
7 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
8 * Copyright (C) 2001 Ralf Baechle
9 * Copyright (C) 2013 Imagination Technologies Ltd.
10 *
11 * Routines for generic manipulation of the interrupts found on the MIPS
12 * Malta board. The interrupt controller is located in the South Bridge
13 * a PIIX4 device with two internal 82C95 interrupt controllers.
14 */
15#include <linux/init.h>
16#include <linux/irq.h>
17#include <linux/sched.h>
18#include <linux/smp.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/irqchip/mips-gic.h>
22#include <linux/kernel_stat.h>
23#include <linux/kernel.h>
24#include <linux/random.h>
25
26#include <asm/traps.h>
27#include <asm/i8259.h>
28#include <asm/irq_cpu.h>
29#include <asm/irq_regs.h>
30#include <asm/mips-cm.h>
31#include <asm/mips-boards/malta.h>
32#include <asm/mips-boards/maltaint.h>
33#include <asm/gt64120.h>
34#include <asm/mips-boards/generic.h>
35#include <asm/mips-boards/msc01_pci.h>
36#include <asm/msc01_ic.h>
37#include <asm/setup.h>
38#include <asm/rtlx.h>
39
40static void __iomem *_msc01_biu_base;
41
42static DEFINE_RAW_SPINLOCK(mips_irq_lock);
43
44static inline int mips_pcibios_iack(void)
45{
46	int irq;
47
48	/*
49	 * Determine highest priority pending interrupt by performing
50	 * a PCI Interrupt Acknowledge cycle.
51	 */
52	switch (mips_revision_sconid) {
53	case MIPS_REVISION_SCON_SOCIT:
54	case MIPS_REVISION_SCON_ROCIT:
55	case MIPS_REVISION_SCON_SOCITSC:
56	case MIPS_REVISION_SCON_SOCITSCP:
57		MSC_READ(MSC01_PCI_IACK, irq);
58		irq &= 0xff;
59		break;
60	case MIPS_REVISION_SCON_GT64120:
61		irq = GT_READ(GT_PCI0_IACK_OFS);
62		irq &= 0xff;
63		break;
64	case MIPS_REVISION_SCON_BONITO:
65		/* The following will generate a PCI IACK cycle on the
66		 * Bonito controller. It's a little bit kludgy, but it
67		 * was the easiest way to implement it in hardware at
68		 * the given time.
69		 */
70		BONITO_PCIMAP_CFG = 0x20000;
71
72		/* Flush Bonito register block */
73		(void) BONITO_PCIMAP_CFG;
74		iob();	  /* sync */
75
76		irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
77		iob();	  /* sync */
78		irq &= 0xff;
79		BONITO_PCIMAP_CFG = 0;
80		break;
81	default:
82		pr_emerg("Unknown system controller.\n");
83		return -1;
84	}
85	return irq;
86}
87
88static inline int get_int(void)
89{
90	unsigned long flags;
91	int irq;
92	raw_spin_lock_irqsave(&mips_irq_lock, flags);
93
94	irq = mips_pcibios_iack();
95
96	/*
97	 * The only way we can decide if an interrupt is spurious
98	 * is by checking the 8259 registers.  This needs a spinlock
99	 * on an SMP system,  so leave it up to the generic code...
100	 */
101
102	raw_spin_unlock_irqrestore(&mips_irq_lock, flags);
103
104	return irq;
105}
106
107static void malta_hw0_irqdispatch(void)
108{
109	int irq;
110
111	irq = get_int();
112	if (irq < 0) {
113		/* interrupt has already been cleared */
114		return;
115	}
116
117	do_IRQ(MALTA_INT_BASE + irq);
118
119#ifdef CONFIG_MIPS_VPE_APSP_API_MT
120	if (aprp_hook)
121		aprp_hook();
122#endif
123}
124
125static irqreturn_t i8259_handler(int irq, void *dev_id)
126{
127	malta_hw0_irqdispatch();
128	return IRQ_HANDLED;
129}
130
131static void corehi_irqdispatch(void)
132{
133	unsigned int intedge, intsteer, pcicmd, pcibadaddr;
134	unsigned int pcimstat, intisr, inten, intpol;
135	unsigned int intrcause, datalo, datahi;
136	struct pt_regs *regs = get_irq_regs();
137
138	pr_emerg("CoreHI interrupt, shouldn't happen, we die here!\n");
139	pr_emerg("epc	 : %08lx\nStatus: %08lx\n"
140		 "Cause : %08lx\nbadVaddr : %08lx\n",
141		 regs->cp0_epc, regs->cp0_status,
142		 regs->cp0_cause, regs->cp0_badvaddr);
143
144	/* Read all the registers and then print them as there is a
145	   problem with interspersed printk's upsetting the Bonito controller.
146	   Do it for the others too.
147	*/
148
149	switch (mips_revision_sconid) {
150	case MIPS_REVISION_SCON_SOCIT:
151	case MIPS_REVISION_SCON_ROCIT:
152	case MIPS_REVISION_SCON_SOCITSC:
153	case MIPS_REVISION_SCON_SOCITSCP:
154		ll_msc_irq();
155		break;
156	case MIPS_REVISION_SCON_GT64120:
157		intrcause = GT_READ(GT_INTRCAUSE_OFS);
158		datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
159		datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
160		pr_emerg("GT_INTRCAUSE = %08x\n", intrcause);
161		pr_emerg("GT_CPUERR_ADDR = %02x%08x\n",
162				datahi, datalo);
163		break;
164	case MIPS_REVISION_SCON_BONITO:
165		pcibadaddr = BONITO_PCIBADADDR;
166		pcimstat = BONITO_PCIMSTAT;
167		intisr = BONITO_INTISR;
168		inten = BONITO_INTEN;
169		intpol = BONITO_INTPOL;
170		intedge = BONITO_INTEDGE;
171		intsteer = BONITO_INTSTEER;
172		pcicmd = BONITO_PCICMD;
173		pr_emerg("BONITO_INTISR = %08x\n", intisr);
174		pr_emerg("BONITO_INTEN = %08x\n", inten);
175		pr_emerg("BONITO_INTPOL = %08x\n", intpol);
176		pr_emerg("BONITO_INTEDGE = %08x\n", intedge);
177		pr_emerg("BONITO_INTSTEER = %08x\n", intsteer);
178		pr_emerg("BONITO_PCICMD = %08x\n", pcicmd);
179		pr_emerg("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
180		pr_emerg("BONITO_PCIMSTAT = %08x\n", pcimstat);
181		break;
182	}
183
184	die("CoreHi interrupt", regs);
185}
186
187static irqreturn_t corehi_handler(int irq, void *dev_id)
188{
189	corehi_irqdispatch();
190	return IRQ_HANDLED;
191}
192
193#ifdef CONFIG_MIPS_MT_SMP
194
195#define MIPS_CPU_IPI_RESCHED_IRQ 0	/* SW int 0 for resched */
196#define C_RESCHED C_SW0
197#define MIPS_CPU_IPI_CALL_IRQ 1		/* SW int 1 for resched */
198#define C_CALL C_SW1
199static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
200
201static void ipi_resched_dispatch(void)
202{
203	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
204}
205
206static void ipi_call_dispatch(void)
207{
208	do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
209}
210
211static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
212{
213#ifdef CONFIG_MIPS_VPE_APSP_API_CMP
214	if (aprp_hook)
215		aprp_hook();
216#endif
217
218	scheduler_ipi();
219
220	return IRQ_HANDLED;
221}
222
223static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
224{
225	smp_call_function_interrupt();
226
227	return IRQ_HANDLED;
228}
229
230static struct irqaction irq_resched = {
231	.handler	= ipi_resched_interrupt,
232	.flags		= IRQF_PERCPU,
233	.name		= "IPI_resched"
234};
235
236static struct irqaction irq_call = {
237	.handler	= ipi_call_interrupt,
238	.flags		= IRQF_PERCPU,
239	.name		= "IPI_call"
240};
241#endif /* CONFIG_MIPS_MT_SMP */
242
243static struct irqaction i8259irq = {
244	.handler = i8259_handler,
245	.name = "XT-PIC cascade",
246	.flags = IRQF_NO_THREAD,
247};
248
249static struct irqaction corehi_irqaction = {
250	.handler = corehi_handler,
251	.name = "CoreHi",
252	.flags = IRQF_NO_THREAD,
253};
254
255static msc_irqmap_t msc_irqmap[] __initdata = {
256	{MSC01C_INT_TMR,		MSC01_IRQ_EDGE, 0},
257	{MSC01C_INT_PCI,		MSC01_IRQ_LEVEL, 0},
258};
259static int msc_nr_irqs __initdata = ARRAY_SIZE(msc_irqmap);
260
261static msc_irqmap_t msc_eicirqmap[] __initdata = {
262	{MSC01E_INT_SW0,		MSC01_IRQ_LEVEL, 0},
263	{MSC01E_INT_SW1,		MSC01_IRQ_LEVEL, 0},
264	{MSC01E_INT_I8259A,		MSC01_IRQ_LEVEL, 0},
265	{MSC01E_INT_SMI,		MSC01_IRQ_LEVEL, 0},
266	{MSC01E_INT_COREHI,		MSC01_IRQ_LEVEL, 0},
267	{MSC01E_INT_CORELO,		MSC01_IRQ_LEVEL, 0},
268	{MSC01E_INT_TMR,		MSC01_IRQ_EDGE, 0},
269	{MSC01E_INT_PCI,		MSC01_IRQ_LEVEL, 0},
270	{MSC01E_INT_PERFCTR,		MSC01_IRQ_LEVEL, 0},
271	{MSC01E_INT_CPUCTR,		MSC01_IRQ_LEVEL, 0}
272};
273
274static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap);
275
276void __init arch_init_ipiirq(int irq, struct irqaction *action)
277{
278	setup_irq(irq, action);
279	irq_set_handler(irq, handle_percpu_irq);
280}
281
282void __init arch_init_irq(void)
283{
284	int corehi_irq, i8259_irq;
285
286	init_i8259_irqs();
287
288	if (!cpu_has_veic)
289		mips_cpu_irq_init();
290
291	if (mips_cm_present()) {
292		write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK);
293		gic_present = 1;
294	} else {
295		if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
296			_msc01_biu_base = ioremap_nocache(MSC01_BIU_REG_BASE,
297						MSC01_BIU_ADDRSPACE_SZ);
298			gic_present =
299			  (__raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS) &
300			   MSC01_SC_CFG_GICPRES_MSK) >>
301			  MSC01_SC_CFG_GICPRES_SHF;
302		}
303	}
304	if (gic_present)
305		pr_debug("GIC present\n");
306
307	switch (mips_revision_sconid) {
308	case MIPS_REVISION_SCON_SOCIT:
309	case MIPS_REVISION_SCON_ROCIT:
310		if (cpu_has_veic)
311			init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
312					MSC01E_INT_BASE, msc_eicirqmap,
313					msc_nr_eicirqs);
314		else
315			init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
316					MSC01C_INT_BASE, msc_irqmap,
317					msc_nr_irqs);
318		break;
319
320	case MIPS_REVISION_SCON_SOCITSC:
321	case MIPS_REVISION_SCON_SOCITSCP:
322		if (cpu_has_veic)
323			init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
324					MSC01E_INT_BASE, msc_eicirqmap,
325					msc_nr_eicirqs);
326		else
327			init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
328					MSC01C_INT_BASE, msc_irqmap,
329					msc_nr_irqs);
330	}
331
332	if (gic_present) {
333		int i;
334
335		gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, MIPSCPU_INT_GIC,
336			 MIPS_GIC_IRQ_BASE);
337		if (!mips_cm_present()) {
338			/* Enable the GIC */
339			i = __raw_readl(_msc01_biu_base + MSC01_SC_CFG_OFS);
340			__raw_writel(i | (0x1 << MSC01_SC_CFG_GICENA_SHF),
341				 _msc01_biu_base + MSC01_SC_CFG_OFS);
342			pr_debug("GIC Enabled\n");
343		}
344		i8259_irq = MIPS_GIC_IRQ_BASE + GIC_INT_I8259A;
345		corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
346	} else {
347#if defined(CONFIG_MIPS_MT_SMP)
348		/* set up ipi interrupts */
349		if (cpu_has_veic) {
350			set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
351			set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch);
352			cpu_ipi_resched_irq = MSC01E_INT_SW0;
353			cpu_ipi_call_irq = MSC01E_INT_SW1;
354		} else {
355			cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE +
356				MIPS_CPU_IPI_RESCHED_IRQ;
357			cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE +
358				MIPS_CPU_IPI_CALL_IRQ;
359		}
360		arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
361		arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
362#endif
363		if (cpu_has_veic) {
364			set_vi_handler(MSC01E_INT_I8259A,
365				       malta_hw0_irqdispatch);
366			set_vi_handler(MSC01E_INT_COREHI,
367				       corehi_irqdispatch);
368			i8259_irq = MSC01E_INT_BASE + MSC01E_INT_I8259A;
369			corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI;
370		} else {
371			i8259_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_I8259A;
372			corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
373		}
374	}
375
376	setup_irq(i8259_irq, &i8259irq);
377	setup_irq(corehi_irq, &corehi_irqaction);
378}
379
380void malta_be_init(void)
381{
382	/* Could change CM error mask register. */
383}
384
385
386static char *tr[8] = {
387	"mem",	"gcr",	"gic",	"mmio",
388	"0x04", "0x05", "0x06", "0x07"
389};
390
391static char *mcmd[32] = {
392	[0x00] = "0x00",
393	[0x01] = "Legacy Write",
394	[0x02] = "Legacy Read",
395	[0x03] = "0x03",
396	[0x04] = "0x04",
397	[0x05] = "0x05",
398	[0x06] = "0x06",
399	[0x07] = "0x07",
400	[0x08] = "Coherent Read Own",
401	[0x09] = "Coherent Read Share",
402	[0x0a] = "Coherent Read Discard",
403	[0x0b] = "Coherent Ready Share Always",
404	[0x0c] = "Coherent Upgrade",
405	[0x0d] = "Coherent Writeback",
406	[0x0e] = "0x0e",
407	[0x0f] = "0x0f",
408	[0x10] = "Coherent Copyback",
409	[0x11] = "Coherent Copyback Invalidate",
410	[0x12] = "Coherent Invalidate",
411	[0x13] = "Coherent Write Invalidate",
412	[0x14] = "Coherent Completion Sync",
413	[0x15] = "0x15",
414	[0x16] = "0x16",
415	[0x17] = "0x17",
416	[0x18] = "0x18",
417	[0x19] = "0x19",
418	[0x1a] = "0x1a",
419	[0x1b] = "0x1b",
420	[0x1c] = "0x1c",
421	[0x1d] = "0x1d",
422	[0x1e] = "0x1e",
423	[0x1f] = "0x1f"
424};
425
426static char *core[8] = {
427	"Invalid/OK",	"Invalid/Data",
428	"Shared/OK",	"Shared/Data",
429	"Modified/OK",	"Modified/Data",
430	"Exclusive/OK", "Exclusive/Data"
431};
432
433static char *causes[32] = {
434	"None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
435	"COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
436	"0x08", "0x09", "0x0a", "0x0b",
437	"0x0c", "0x0d", "0x0e", "0x0f",
438	"0x10", "0x11", "0x12", "0x13",
439	"0x14", "0x15", "0x16", "INTVN_WR_ERR",
440	"INTVN_RD_ERR", "0x19", "0x1a", "0x1b",
441	"0x1c", "0x1d", "0x1e", "0x1f"
442};
443
444int malta_be_handler(struct pt_regs *regs, int is_fixup)
445{
446	/* This duplicates the handling in do_be which seems wrong */
447	int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
448
449	if (mips_cm_present()) {
450		unsigned long cm_error = read_gcr_error_cause();
451		unsigned long cm_addr = read_gcr_error_addr();
452		unsigned long cm_other = read_gcr_error_mult();
453		unsigned long cause, ocause;
454		char buf[256];
455
456		cause = cm_error & CM_GCR_ERROR_CAUSE_ERRTYPE_MSK;
457		if (cause != 0) {
458			cause >>= CM_GCR_ERROR_CAUSE_ERRTYPE_SHF;
459			if (cause < 16) {
460				unsigned long cca_bits = (cm_error >> 15) & 7;
461				unsigned long tr_bits = (cm_error >> 12) & 7;
462				unsigned long cmd_bits = (cm_error >> 7) & 0x1f;
463				unsigned long stag_bits = (cm_error >> 3) & 15;
464				unsigned long sport_bits = (cm_error >> 0) & 7;
465
466				snprintf(buf, sizeof(buf),
467					 "CCA=%lu TR=%s MCmd=%s STag=%lu "
468					 "SPort=%lu\n",
469					 cca_bits, tr[tr_bits], mcmd[cmd_bits],
470					 stag_bits, sport_bits);
471			} else {
472				/* glob state & sresp together */
473				unsigned long c3_bits = (cm_error >> 18) & 7;
474				unsigned long c2_bits = (cm_error >> 15) & 7;
475				unsigned long c1_bits = (cm_error >> 12) & 7;
476				unsigned long c0_bits = (cm_error >> 9) & 7;
477				unsigned long sc_bit = (cm_error >> 8) & 1;
478				unsigned long cmd_bits = (cm_error >> 3) & 0x1f;
479				unsigned long sport_bits = (cm_error >> 0) & 7;
480				snprintf(buf, sizeof(buf),
481					 "C3=%s C2=%s C1=%s C0=%s SC=%s "
482					 "MCmd=%s SPort=%lu\n",
483					 core[c3_bits], core[c2_bits],
484					 core[c1_bits], core[c0_bits],
485					 sc_bit ? "True" : "False",
486					 mcmd[cmd_bits], sport_bits);
487			}
488
489			ocause = (cm_other & CM_GCR_ERROR_MULT_ERR2ND_MSK) >>
490				 CM_GCR_ERROR_MULT_ERR2ND_SHF;
491
492			pr_err("CM_ERROR=%08lx %s <%s>\n", cm_error,
493			       causes[cause], buf);
494			pr_err("CM_ADDR =%08lx\n", cm_addr);
495			pr_err("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]);
496
497			/* reprime cause register */
498			write_gcr_error_cause(0);
499		}
500	}
501
502	return retval;
503}
504