1/* 2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator 3 * 4 * MIPS floating point support 5 * Copyright (C) 1994-2000 Algorithmics Ltd. 6 * 7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 8 * Copyright (C) 2000 MIPS Technologies, Inc. 9 * 10 * This program is free software; you can distribute it and/or modify it 11 * under the terms of the GNU General Public License (Version 2) as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, write to the Free Software Foundation, Inc., 21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 22 * 23 * A complete emulator for MIPS coprocessor 1 instructions. This is 24 * required for #float(switch) or #float(trap), where it catches all 25 * COP1 instructions via the "CoProcessor Unusable" exception. 26 * 27 * More surprisingly it is also required for #float(ieee), to help out 28 * the hardware FPU at the boundaries of the IEEE-754 representation 29 * (denormalised values, infinities, underflow, etc). It is made 30 * quite nasty because emulation of some non-COP1 instructions is 31 * required, e.g. in branch delay slots. 32 * 33 * Note if you know that you won't have an FPU, then you'll get much 34 * better performance by compiling with -msoft-float! 35 */ 36#include <linux/sched.h> 37#include <linux/debugfs.h> 38#include <linux/kconfig.h> 39#include <linux/percpu-defs.h> 40#include <linux/perf_event.h> 41 42#include <asm/branch.h> 43#include <asm/inst.h> 44#include <asm/ptrace.h> 45#include <asm/signal.h> 46#include <asm/uaccess.h> 47 48#include <asm/cpu-info.h> 49#include <asm/processor.h> 50#include <asm/fpu_emulator.h> 51#include <asm/fpu.h> 52#include <asm/mips-r2-to-r6-emul.h> 53 54#include "ieee754.h" 55 56/* Function which emulates a floating point instruction. */ 57 58static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, 59 mips_instruction); 60 61static int fpux_emu(struct pt_regs *, 62 struct mips_fpu_struct *, mips_instruction, void *__user *); 63 64/* Control registers */ 65 66#define FPCREG_RID 0 /* $0 = revision id */ 67#define FPCREG_FCCR 25 /* $25 = fccr */ 68#define FPCREG_FEXR 26 /* $26 = fexr */ 69#define FPCREG_FENR 28 /* $28 = fenr */ 70#define FPCREG_CSR 31 /* $31 = csr */ 71 72/* convert condition code register number to csr bit */ 73const unsigned int fpucondbit[8] = { 74 FPU_CSR_COND, 75 FPU_CSR_COND1, 76 FPU_CSR_COND2, 77 FPU_CSR_COND3, 78 FPU_CSR_COND4, 79 FPU_CSR_COND5, 80 FPU_CSR_COND6, 81 FPU_CSR_COND7 82}; 83 84/* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ 85static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; 86static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; 87static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; 88static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; 89 90/* 91 * This functions translates a 32-bit microMIPS instruction 92 * into a 32-bit MIPS32 instruction. Returns 0 on success 93 * and SIGILL otherwise. 94 */ 95static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) 96{ 97 union mips_instruction insn = *insn_ptr; 98 union mips_instruction mips32_insn = insn; 99 int func, fmt, op; 100 101 switch (insn.mm_i_format.opcode) { 102 case mm_ldc132_op: 103 mips32_insn.mm_i_format.opcode = ldc1_op; 104 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 105 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 106 break; 107 case mm_lwc132_op: 108 mips32_insn.mm_i_format.opcode = lwc1_op; 109 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 110 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 111 break; 112 case mm_sdc132_op: 113 mips32_insn.mm_i_format.opcode = sdc1_op; 114 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 115 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 116 break; 117 case mm_swc132_op: 118 mips32_insn.mm_i_format.opcode = swc1_op; 119 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 120 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 121 break; 122 case mm_pool32i_op: 123 /* NOTE: offset is << by 1 if in microMIPS mode. */ 124 if ((insn.mm_i_format.rt == mm_bc1f_op) || 125 (insn.mm_i_format.rt == mm_bc1t_op)) { 126 mips32_insn.fb_format.opcode = cop1_op; 127 mips32_insn.fb_format.bc = bc_op; 128 mips32_insn.fb_format.flag = 129 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; 130 } else 131 return SIGILL; 132 break; 133 case mm_pool32f_op: 134 switch (insn.mm_fp0_format.func) { 135 case mm_32f_01_op: 136 case mm_32f_11_op: 137 case mm_32f_02_op: 138 case mm_32f_12_op: 139 case mm_32f_41_op: 140 case mm_32f_51_op: 141 case mm_32f_42_op: 142 case mm_32f_52_op: 143 op = insn.mm_fp0_format.func; 144 if (op == mm_32f_01_op) 145 func = madd_s_op; 146 else if (op == mm_32f_11_op) 147 func = madd_d_op; 148 else if (op == mm_32f_02_op) 149 func = nmadd_s_op; 150 else if (op == mm_32f_12_op) 151 func = nmadd_d_op; 152 else if (op == mm_32f_41_op) 153 func = msub_s_op; 154 else if (op == mm_32f_51_op) 155 func = msub_d_op; 156 else if (op == mm_32f_42_op) 157 func = nmsub_s_op; 158 else 159 func = nmsub_d_op; 160 mips32_insn.fp6_format.opcode = cop1x_op; 161 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; 162 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; 163 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; 164 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; 165 mips32_insn.fp6_format.func = func; 166 break; 167 case mm_32f_10_op: 168 func = -1; /* Invalid */ 169 op = insn.mm_fp5_format.op & 0x7; 170 if (op == mm_ldxc1_op) 171 func = ldxc1_op; 172 else if (op == mm_sdxc1_op) 173 func = sdxc1_op; 174 else if (op == mm_lwxc1_op) 175 func = lwxc1_op; 176 else if (op == mm_swxc1_op) 177 func = swxc1_op; 178 179 if (func != -1) { 180 mips32_insn.r_format.opcode = cop1x_op; 181 mips32_insn.r_format.rs = 182 insn.mm_fp5_format.base; 183 mips32_insn.r_format.rt = 184 insn.mm_fp5_format.index; 185 mips32_insn.r_format.rd = 0; 186 mips32_insn.r_format.re = insn.mm_fp5_format.fd; 187 mips32_insn.r_format.func = func; 188 } else 189 return SIGILL; 190 break; 191 case mm_32f_40_op: 192 op = -1; /* Invalid */ 193 if (insn.mm_fp2_format.op == mm_fmovt_op) 194 op = 1; 195 else if (insn.mm_fp2_format.op == mm_fmovf_op) 196 op = 0; 197 if (op != -1) { 198 mips32_insn.fp0_format.opcode = cop1_op; 199 mips32_insn.fp0_format.fmt = 200 sdps_format[insn.mm_fp2_format.fmt]; 201 mips32_insn.fp0_format.ft = 202 (insn.mm_fp2_format.cc<<2) + op; 203 mips32_insn.fp0_format.fs = 204 insn.mm_fp2_format.fs; 205 mips32_insn.fp0_format.fd = 206 insn.mm_fp2_format.fd; 207 mips32_insn.fp0_format.func = fmovc_op; 208 } else 209 return SIGILL; 210 break; 211 case mm_32f_60_op: 212 func = -1; /* Invalid */ 213 if (insn.mm_fp0_format.op == mm_fadd_op) 214 func = fadd_op; 215 else if (insn.mm_fp0_format.op == mm_fsub_op) 216 func = fsub_op; 217 else if (insn.mm_fp0_format.op == mm_fmul_op) 218 func = fmul_op; 219 else if (insn.mm_fp0_format.op == mm_fdiv_op) 220 func = fdiv_op; 221 if (func != -1) { 222 mips32_insn.fp0_format.opcode = cop1_op; 223 mips32_insn.fp0_format.fmt = 224 sdps_format[insn.mm_fp0_format.fmt]; 225 mips32_insn.fp0_format.ft = 226 insn.mm_fp0_format.ft; 227 mips32_insn.fp0_format.fs = 228 insn.mm_fp0_format.fs; 229 mips32_insn.fp0_format.fd = 230 insn.mm_fp0_format.fd; 231 mips32_insn.fp0_format.func = func; 232 } else 233 return SIGILL; 234 break; 235 case mm_32f_70_op: 236 func = -1; /* Invalid */ 237 if (insn.mm_fp0_format.op == mm_fmovn_op) 238 func = fmovn_op; 239 else if (insn.mm_fp0_format.op == mm_fmovz_op) 240 func = fmovz_op; 241 if (func != -1) { 242 mips32_insn.fp0_format.opcode = cop1_op; 243 mips32_insn.fp0_format.fmt = 244 sdps_format[insn.mm_fp0_format.fmt]; 245 mips32_insn.fp0_format.ft = 246 insn.mm_fp0_format.ft; 247 mips32_insn.fp0_format.fs = 248 insn.mm_fp0_format.fs; 249 mips32_insn.fp0_format.fd = 250 insn.mm_fp0_format.fd; 251 mips32_insn.fp0_format.func = func; 252 } else 253 return SIGILL; 254 break; 255 case mm_32f_73_op: /* POOL32FXF */ 256 switch (insn.mm_fp1_format.op) { 257 case mm_movf0_op: 258 case mm_movf1_op: 259 case mm_movt0_op: 260 case mm_movt1_op: 261 if ((insn.mm_fp1_format.op & 0x7f) == 262 mm_movf0_op) 263 op = 0; 264 else 265 op = 1; 266 mips32_insn.r_format.opcode = spec_op; 267 mips32_insn.r_format.rs = insn.mm_fp4_format.fs; 268 mips32_insn.r_format.rt = 269 (insn.mm_fp4_format.cc << 2) + op; 270 mips32_insn.r_format.rd = insn.mm_fp4_format.rt; 271 mips32_insn.r_format.re = 0; 272 mips32_insn.r_format.func = movc_op; 273 break; 274 case mm_fcvtd0_op: 275 case mm_fcvtd1_op: 276 case mm_fcvts0_op: 277 case mm_fcvts1_op: 278 if ((insn.mm_fp1_format.op & 0x7f) == 279 mm_fcvtd0_op) { 280 func = fcvtd_op; 281 fmt = swl_format[insn.mm_fp3_format.fmt]; 282 } else { 283 func = fcvts_op; 284 fmt = dwl_format[insn.mm_fp3_format.fmt]; 285 } 286 mips32_insn.fp0_format.opcode = cop1_op; 287 mips32_insn.fp0_format.fmt = fmt; 288 mips32_insn.fp0_format.ft = 0; 289 mips32_insn.fp0_format.fs = 290 insn.mm_fp3_format.fs; 291 mips32_insn.fp0_format.fd = 292 insn.mm_fp3_format.rt; 293 mips32_insn.fp0_format.func = func; 294 break; 295 case mm_fmov0_op: 296 case mm_fmov1_op: 297 case mm_fabs0_op: 298 case mm_fabs1_op: 299 case mm_fneg0_op: 300 case mm_fneg1_op: 301 if ((insn.mm_fp1_format.op & 0x7f) == 302 mm_fmov0_op) 303 func = fmov_op; 304 else if ((insn.mm_fp1_format.op & 0x7f) == 305 mm_fabs0_op) 306 func = fabs_op; 307 else 308 func = fneg_op; 309 mips32_insn.fp0_format.opcode = cop1_op; 310 mips32_insn.fp0_format.fmt = 311 sdps_format[insn.mm_fp3_format.fmt]; 312 mips32_insn.fp0_format.ft = 0; 313 mips32_insn.fp0_format.fs = 314 insn.mm_fp3_format.fs; 315 mips32_insn.fp0_format.fd = 316 insn.mm_fp3_format.rt; 317 mips32_insn.fp0_format.func = func; 318 break; 319 case mm_ffloorl_op: 320 case mm_ffloorw_op: 321 case mm_fceill_op: 322 case mm_fceilw_op: 323 case mm_ftruncl_op: 324 case mm_ftruncw_op: 325 case mm_froundl_op: 326 case mm_froundw_op: 327 case mm_fcvtl_op: 328 case mm_fcvtw_op: 329 if (insn.mm_fp1_format.op == mm_ffloorl_op) 330 func = ffloorl_op; 331 else if (insn.mm_fp1_format.op == mm_ffloorw_op) 332 func = ffloor_op; 333 else if (insn.mm_fp1_format.op == mm_fceill_op) 334 func = fceill_op; 335 else if (insn.mm_fp1_format.op == mm_fceilw_op) 336 func = fceil_op; 337 else if (insn.mm_fp1_format.op == mm_ftruncl_op) 338 func = ftruncl_op; 339 else if (insn.mm_fp1_format.op == mm_ftruncw_op) 340 func = ftrunc_op; 341 else if (insn.mm_fp1_format.op == mm_froundl_op) 342 func = froundl_op; 343 else if (insn.mm_fp1_format.op == mm_froundw_op) 344 func = fround_op; 345 else if (insn.mm_fp1_format.op == mm_fcvtl_op) 346 func = fcvtl_op; 347 else 348 func = fcvtw_op; 349 mips32_insn.fp0_format.opcode = cop1_op; 350 mips32_insn.fp0_format.fmt = 351 sd_format[insn.mm_fp1_format.fmt]; 352 mips32_insn.fp0_format.ft = 0; 353 mips32_insn.fp0_format.fs = 354 insn.mm_fp1_format.fs; 355 mips32_insn.fp0_format.fd = 356 insn.mm_fp1_format.rt; 357 mips32_insn.fp0_format.func = func; 358 break; 359 case mm_frsqrt_op: 360 case mm_fsqrt_op: 361 case mm_frecip_op: 362 if (insn.mm_fp1_format.op == mm_frsqrt_op) 363 func = frsqrt_op; 364 else if (insn.mm_fp1_format.op == mm_fsqrt_op) 365 func = fsqrt_op; 366 else 367 func = frecip_op; 368 mips32_insn.fp0_format.opcode = cop1_op; 369 mips32_insn.fp0_format.fmt = 370 sdps_format[insn.mm_fp1_format.fmt]; 371 mips32_insn.fp0_format.ft = 0; 372 mips32_insn.fp0_format.fs = 373 insn.mm_fp1_format.fs; 374 mips32_insn.fp0_format.fd = 375 insn.mm_fp1_format.rt; 376 mips32_insn.fp0_format.func = func; 377 break; 378 case mm_mfc1_op: 379 case mm_mtc1_op: 380 case mm_cfc1_op: 381 case mm_ctc1_op: 382 case mm_mfhc1_op: 383 case mm_mthc1_op: 384 if (insn.mm_fp1_format.op == mm_mfc1_op) 385 op = mfc_op; 386 else if (insn.mm_fp1_format.op == mm_mtc1_op) 387 op = mtc_op; 388 else if (insn.mm_fp1_format.op == mm_cfc1_op) 389 op = cfc_op; 390 else if (insn.mm_fp1_format.op == mm_ctc1_op) 391 op = ctc_op; 392 else if (insn.mm_fp1_format.op == mm_mfhc1_op) 393 op = mfhc_op; 394 else 395 op = mthc_op; 396 mips32_insn.fp1_format.opcode = cop1_op; 397 mips32_insn.fp1_format.op = op; 398 mips32_insn.fp1_format.rt = 399 insn.mm_fp1_format.rt; 400 mips32_insn.fp1_format.fs = 401 insn.mm_fp1_format.fs; 402 mips32_insn.fp1_format.fd = 0; 403 mips32_insn.fp1_format.func = 0; 404 break; 405 default: 406 return SIGILL; 407 } 408 break; 409 case mm_32f_74_op: /* c.cond.fmt */ 410 mips32_insn.fp0_format.opcode = cop1_op; 411 mips32_insn.fp0_format.fmt = 412 sdps_format[insn.mm_fp4_format.fmt]; 413 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; 414 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; 415 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; 416 mips32_insn.fp0_format.func = 417 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; 418 break; 419 default: 420 return SIGILL; 421 } 422 break; 423 default: 424 return SIGILL; 425 } 426 427 *insn_ptr = mips32_insn; 428 return 0; 429} 430 431/* 432 * Redundant with logic already in kernel/branch.c, 433 * embedded in compute_return_epc. At some point, 434 * a single subroutine should be used across both 435 * modules. 436 */ 437static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 438 unsigned long *contpc) 439{ 440 union mips_instruction insn = (union mips_instruction)dec_insn.insn; 441 unsigned int fcr31; 442 unsigned int bit = 0; 443 444 switch (insn.i_format.opcode) { 445 case spec_op: 446 switch (insn.r_format.func) { 447 case jalr_op: 448 if (insn.r_format.rd != 0) { 449 regs->regs[insn.r_format.rd] = 450 regs->cp0_epc + dec_insn.pc_inc + 451 dec_insn.next_pc_inc; 452 } 453 /* Fall through */ 454 case jr_op: 455 /* For R6, JR already emulated in jalr_op */ 456 if (NO_R6EMU && insn.r_format.func == jr_op) 457 break; 458 *contpc = regs->regs[insn.r_format.rs]; 459 return 1; 460 } 461 break; 462 case bcond_op: 463 switch (insn.i_format.rt) { 464 case bltzal_op: 465 case bltzall_op: 466 if (NO_R6EMU && (insn.i_format.rs || 467 insn.i_format.rt == bltzall_op)) 468 break; 469 470 regs->regs[31] = regs->cp0_epc + 471 dec_insn.pc_inc + 472 dec_insn.next_pc_inc; 473 /* Fall through */ 474 case bltzl_op: 475 if (NO_R6EMU) 476 break; 477 case bltz_op: 478 if ((long)regs->regs[insn.i_format.rs] < 0) 479 *contpc = regs->cp0_epc + 480 dec_insn.pc_inc + 481 (insn.i_format.simmediate << 2); 482 else 483 *contpc = regs->cp0_epc + 484 dec_insn.pc_inc + 485 dec_insn.next_pc_inc; 486 return 1; 487 case bgezal_op: 488 case bgezall_op: 489 if (NO_R6EMU && (insn.i_format.rs || 490 insn.i_format.rt == bgezall_op)) 491 break; 492 493 regs->regs[31] = regs->cp0_epc + 494 dec_insn.pc_inc + 495 dec_insn.next_pc_inc; 496 /* Fall through */ 497 case bgezl_op: 498 if (NO_R6EMU) 499 break; 500 case bgez_op: 501 if ((long)regs->regs[insn.i_format.rs] >= 0) 502 *contpc = regs->cp0_epc + 503 dec_insn.pc_inc + 504 (insn.i_format.simmediate << 2); 505 else 506 *contpc = regs->cp0_epc + 507 dec_insn.pc_inc + 508 dec_insn.next_pc_inc; 509 return 1; 510 } 511 break; 512 case jalx_op: 513 set_isa16_mode(bit); 514 case jal_op: 515 regs->regs[31] = regs->cp0_epc + 516 dec_insn.pc_inc + 517 dec_insn.next_pc_inc; 518 /* Fall through */ 519 case j_op: 520 *contpc = regs->cp0_epc + dec_insn.pc_inc; 521 *contpc >>= 28; 522 *contpc <<= 28; 523 *contpc |= (insn.j_format.target << 2); 524 /* Set microMIPS mode bit: XOR for jalx. */ 525 *contpc ^= bit; 526 return 1; 527 case beql_op: 528 if (NO_R6EMU) 529 break; 530 case beq_op: 531 if (regs->regs[insn.i_format.rs] == 532 regs->regs[insn.i_format.rt]) 533 *contpc = regs->cp0_epc + 534 dec_insn.pc_inc + 535 (insn.i_format.simmediate << 2); 536 else 537 *contpc = regs->cp0_epc + 538 dec_insn.pc_inc + 539 dec_insn.next_pc_inc; 540 return 1; 541 case bnel_op: 542 if (NO_R6EMU) 543 break; 544 case bne_op: 545 if (regs->regs[insn.i_format.rs] != 546 regs->regs[insn.i_format.rt]) 547 *contpc = regs->cp0_epc + 548 dec_insn.pc_inc + 549 (insn.i_format.simmediate << 2); 550 else 551 *contpc = regs->cp0_epc + 552 dec_insn.pc_inc + 553 dec_insn.next_pc_inc; 554 return 1; 555 case blezl_op: 556 if (NO_R6EMU) 557 break; 558 case blez_op: 559 560 /* 561 * Compact branches for R6 for the 562 * blez and blezl opcodes. 563 * BLEZ | rs = 0 | rt != 0 == BLEZALC 564 * BLEZ | rs = rt != 0 == BGEZALC 565 * BLEZ | rs != 0 | rt != 0 == BGEUC 566 * BLEZL | rs = 0 | rt != 0 == BLEZC 567 * BLEZL | rs = rt != 0 == BGEZC 568 * BLEZL | rs != 0 | rt != 0 == BGEC 569 * 570 * For real BLEZ{,L}, rt is always 0. 571 */ 572 if (cpu_has_mips_r6 && insn.i_format.rt) { 573 if ((insn.i_format.opcode == blez_op) && 574 ((!insn.i_format.rs && insn.i_format.rt) || 575 (insn.i_format.rs == insn.i_format.rt))) 576 regs->regs[31] = regs->cp0_epc + 577 dec_insn.pc_inc; 578 *contpc = regs->cp0_epc + dec_insn.pc_inc + 579 dec_insn.next_pc_inc; 580 581 return 1; 582 } 583 if ((long)regs->regs[insn.i_format.rs] <= 0) 584 *contpc = regs->cp0_epc + 585 dec_insn.pc_inc + 586 (insn.i_format.simmediate << 2); 587 else 588 *contpc = regs->cp0_epc + 589 dec_insn.pc_inc + 590 dec_insn.next_pc_inc; 591 return 1; 592 case bgtzl_op: 593 if (NO_R6EMU) 594 break; 595 case bgtz_op: 596 /* 597 * Compact branches for R6 for the 598 * bgtz and bgtzl opcodes. 599 * BGTZ | rs = 0 | rt != 0 == BGTZALC 600 * BGTZ | rs = rt != 0 == BLTZALC 601 * BGTZ | rs != 0 | rt != 0 == BLTUC 602 * BGTZL | rs = 0 | rt != 0 == BGTZC 603 * BGTZL | rs = rt != 0 == BLTZC 604 * BGTZL | rs != 0 | rt != 0 == BLTC 605 * 606 * *ZALC varint for BGTZ &&& rt != 0 607 * For real GTZ{,L}, rt is always 0. 608 */ 609 if (cpu_has_mips_r6 && insn.i_format.rt) { 610 if ((insn.i_format.opcode == blez_op) && 611 ((!insn.i_format.rs && insn.i_format.rt) || 612 (insn.i_format.rs == insn.i_format.rt))) 613 regs->regs[31] = regs->cp0_epc + 614 dec_insn.pc_inc; 615 *contpc = regs->cp0_epc + dec_insn.pc_inc + 616 dec_insn.next_pc_inc; 617 618 return 1; 619 } 620 621 if ((long)regs->regs[insn.i_format.rs] > 0) 622 *contpc = regs->cp0_epc + 623 dec_insn.pc_inc + 624 (insn.i_format.simmediate << 2); 625 else 626 *contpc = regs->cp0_epc + 627 dec_insn.pc_inc + 628 dec_insn.next_pc_inc; 629 return 1; 630 case cbcond0_op: 631 case cbcond1_op: 632 if (!cpu_has_mips_r6) 633 break; 634 if (insn.i_format.rt && !insn.i_format.rs) 635 regs->regs[31] = regs->cp0_epc + 4; 636 *contpc = regs->cp0_epc + dec_insn.pc_inc + 637 dec_insn.next_pc_inc; 638 639 return 1; 640#ifdef CONFIG_CPU_CAVIUM_OCTEON 641 case lwc2_op: /* This is bbit0 on Octeon */ 642 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) 643 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 644 else 645 *contpc = regs->cp0_epc + 8; 646 return 1; 647 case ldc2_op: /* This is bbit032 on Octeon */ 648 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) 649 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 650 else 651 *contpc = regs->cp0_epc + 8; 652 return 1; 653 case swc2_op: /* This is bbit1 on Octeon */ 654 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) 655 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 656 else 657 *contpc = regs->cp0_epc + 8; 658 return 1; 659 case sdc2_op: /* This is bbit132 on Octeon */ 660 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) 661 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 662 else 663 *contpc = regs->cp0_epc + 8; 664 return 1; 665#else 666 case bc6_op: 667 /* 668 * Only valid for MIPS R6 but we can still end up 669 * here from a broken userland so just tell emulator 670 * this is not a branch and let it break later on. 671 */ 672 if (!cpu_has_mips_r6) 673 break; 674 *contpc = regs->cp0_epc + dec_insn.pc_inc + 675 dec_insn.next_pc_inc; 676 677 return 1; 678 case balc6_op: 679 if (!cpu_has_mips_r6) 680 break; 681 regs->regs[31] = regs->cp0_epc + 4; 682 *contpc = regs->cp0_epc + dec_insn.pc_inc + 683 dec_insn.next_pc_inc; 684 685 return 1; 686 case beqzcjic_op: 687 if (!cpu_has_mips_r6) 688 break; 689 *contpc = regs->cp0_epc + dec_insn.pc_inc + 690 dec_insn.next_pc_inc; 691 692 return 1; 693 case bnezcjialc_op: 694 if (!cpu_has_mips_r6) 695 break; 696 if (!insn.i_format.rs) 697 regs->regs[31] = regs->cp0_epc + 4; 698 *contpc = regs->cp0_epc + dec_insn.pc_inc + 699 dec_insn.next_pc_inc; 700 701 return 1; 702#endif 703 case cop0_op: 704 case cop1_op: 705 /* Need to check for R6 bc1nez and bc1eqz branches */ 706 if (cpu_has_mips_r6 && 707 ((insn.i_format.rs == bc1eqz_op) || 708 (insn.i_format.rs == bc1nez_op))) { 709 bit = 0; 710 switch (insn.i_format.rs) { 711 case bc1eqz_op: 712 if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1) 713 bit = 1; 714 break; 715 case bc1nez_op: 716 if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)) 717 bit = 1; 718 break; 719 } 720 if (bit) 721 *contpc = regs->cp0_epc + 722 dec_insn.pc_inc + 723 (insn.i_format.simmediate << 2); 724 else 725 *contpc = regs->cp0_epc + 726 dec_insn.pc_inc + 727 dec_insn.next_pc_inc; 728 729 return 1; 730 } 731 /* R2/R6 compatible cop1 instruction. Fall through */ 732 case cop2_op: 733 case cop1x_op: 734 if (insn.i_format.rs == bc_op) { 735 preempt_disable(); 736 if (is_fpu_owner()) 737 fcr31 = read_32bit_cp1_register(CP1_STATUS); 738 else 739 fcr31 = current->thread.fpu.fcr31; 740 preempt_enable(); 741 742 bit = (insn.i_format.rt >> 2); 743 bit += (bit != 0); 744 bit += 23; 745 switch (insn.i_format.rt & 3) { 746 case 0: /* bc1f */ 747 case 2: /* bc1fl */ 748 if (~fcr31 & (1 << bit)) 749 *contpc = regs->cp0_epc + 750 dec_insn.pc_inc + 751 (insn.i_format.simmediate << 2); 752 else 753 *contpc = regs->cp0_epc + 754 dec_insn.pc_inc + 755 dec_insn.next_pc_inc; 756 return 1; 757 case 1: /* bc1t */ 758 case 3: /* bc1tl */ 759 if (fcr31 & (1 << bit)) 760 *contpc = regs->cp0_epc + 761 dec_insn.pc_inc + 762 (insn.i_format.simmediate << 2); 763 else 764 *contpc = regs->cp0_epc + 765 dec_insn.pc_inc + 766 dec_insn.next_pc_inc; 767 return 1; 768 } 769 } 770 break; 771 } 772 return 0; 773} 774 775/* 776 * In the Linux kernel, we support selection of FPR format on the 777 * basis of the Status.FR bit. If an FPU is not present, the FR bit 778 * is hardwired to zero, which would imply a 32-bit FPU even for 779 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. 780 * FPU emu is slow and bulky and optimizing this function offers fairly 781 * sizeable benefits so we try to be clever and make this function return 782 * a constant whenever possible, that is on 64-bit kernels without O32 783 * compatibility enabled and on 32-bit without 64-bit FPU support. 784 */ 785static inline int cop1_64bit(struct pt_regs *xcp) 786{ 787 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32)) 788 return 1; 789 else if (config_enabled(CONFIG_32BIT) && 790 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT)) 791 return 0; 792 793 return !test_thread_flag(TIF_32BIT_FPREGS); 794} 795 796static inline bool hybrid_fprs(void) 797{ 798 return test_thread_flag(TIF_HYBRID_FPREGS); 799} 800 801#define SIFROMREG(si, x) \ 802do { \ 803 if (cop1_64bit(xcp) && !hybrid_fprs()) \ 804 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \ 805 else \ 806 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ 807} while (0) 808 809#define SITOREG(si, x) \ 810do { \ 811 if (cop1_64bit(xcp) && !hybrid_fprs()) { \ 812 unsigned i; \ 813 set_fpr32(&ctx->fpr[x], 0, si); \ 814 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 815 set_fpr32(&ctx->fpr[x], i, 0); \ 816 } else { \ 817 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ 818 } \ 819} while (0) 820 821#define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1)) 822 823#define SITOHREG(si, x) \ 824do { \ 825 unsigned i; \ 826 set_fpr32(&ctx->fpr[x], 1, si); \ 827 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 828 set_fpr32(&ctx->fpr[x], i, 0); \ 829} while (0) 830 831#define DIFROMREG(di, x) \ 832 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0)) 833 834#define DITOREG(di, x) \ 835do { \ 836 unsigned fpr, i; \ 837 fpr = (x) & ~(cop1_64bit(xcp) == 0); \ 838 set_fpr64(&ctx->fpr[fpr], 0, di); \ 839 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \ 840 set_fpr64(&ctx->fpr[fpr], i, 0); \ 841} while (0) 842 843#define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) 844#define SPTOREG(sp, x) SITOREG((sp).bits, x) 845#define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) 846#define DPTOREG(dp, x) DITOREG((dp).bits, x) 847 848/* 849 * Emulate a CFC1 instruction. 850 */ 851static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 852 mips_instruction ir) 853{ 854 u32 fcr31 = ctx->fcr31; 855 u32 value = 0; 856 857 switch (MIPSInst_RD(ir)) { 858 case FPCREG_CSR: 859 value = fcr31; 860 pr_debug("%p gpr[%d]<-csr=%08x\n", 861 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 862 break; 863 864 case FPCREG_FENR: 865 if (!cpu_has_mips_r) 866 break; 867 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) & 868 MIPS_FENR_FS; 869 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM); 870 pr_debug("%p gpr[%d]<-enr=%08x\n", 871 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 872 break; 873 874 case FPCREG_FEXR: 875 if (!cpu_has_mips_r) 876 break; 877 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S); 878 pr_debug("%p gpr[%d]<-exr=%08x\n", 879 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 880 break; 881 882 case FPCREG_FCCR: 883 if (!cpu_has_mips_r) 884 break; 885 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) & 886 MIPS_FCCR_COND0; 887 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) & 888 (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0); 889 pr_debug("%p gpr[%d]<-ccr=%08x\n", 890 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 891 break; 892 893 case FPCREG_RID: 894 value = boot_cpu_data.fpu_id; 895 break; 896 897 default: 898 break; 899 } 900 901 if (MIPSInst_RT(ir)) 902 xcp->regs[MIPSInst_RT(ir)] = value; 903} 904 905/* 906 * Emulate a CTC1 instruction. 907 */ 908static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 909 mips_instruction ir) 910{ 911 u32 fcr31 = ctx->fcr31; 912 u32 value; 913 u32 mask; 914 915 if (MIPSInst_RT(ir) == 0) 916 value = 0; 917 else 918 value = xcp->regs[MIPSInst_RT(ir)]; 919 920 switch (MIPSInst_RD(ir)) { 921 case FPCREG_CSR: 922 pr_debug("%p gpr[%d]->csr=%08x\n", 923 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 924 925 /* Preserve read-only bits. */ 926 mask = boot_cpu_data.fpu_msk31; 927 fcr31 = (value & ~mask) | (fcr31 & mask); 928 break; 929 930 case FPCREG_FENR: 931 if (!cpu_has_mips_r) 932 break; 933 pr_debug("%p gpr[%d]->enr=%08x\n", 934 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 935 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM); 936 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) & 937 FPU_CSR_FS; 938 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM); 939 break; 940 941 case FPCREG_FEXR: 942 if (!cpu_has_mips_r) 943 break; 944 pr_debug("%p gpr[%d]->exr=%08x\n", 945 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 946 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S); 947 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S); 948 break; 949 950 case FPCREG_FCCR: 951 if (!cpu_has_mips_r) 952 break; 953 pr_debug("%p gpr[%d]->ccr=%08x\n", 954 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); 955 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND); 956 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) & 957 FPU_CSR_COND; 958 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) & 959 FPU_CSR_CONDX; 960 break; 961 962 default: 963 break; 964 } 965 966 ctx->fcr31 = fcr31; 967} 968 969/* 970 * Emulate the single floating point instruction pointed at by EPC. 971 * Two instructions if the instruction is in a branch delay slot. 972 */ 973 974static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 975 struct mm_decoded_insn dec_insn, void *__user *fault_addr) 976{ 977 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; 978 unsigned int cond, cbit; 979 mips_instruction ir; 980 int likely, pc_inc; 981 u32 __user *wva; 982 u64 __user *dva; 983 u32 wval; 984 u64 dval; 985 int sig; 986 987 /* 988 * These are giving gcc a gentle hint about what to expect in 989 * dec_inst in order to do better optimization. 990 */ 991 if (!cpu_has_mmips && dec_insn.micro_mips_mode) 992 unreachable(); 993 994 /* XXX NEC Vr54xx bug workaround */ 995 if (delay_slot(xcp)) { 996 if (dec_insn.micro_mips_mode) { 997 if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) 998 clear_delay_slot(xcp); 999 } else { 1000 if (!isBranchInstr(xcp, dec_insn, &contpc)) 1001 clear_delay_slot(xcp); 1002 } 1003 } 1004 1005 if (delay_slot(xcp)) { 1006 /* 1007 * The instruction to be emulated is in a branch delay slot 1008 * which means that we have to emulate the branch instruction 1009 * BEFORE we do the cop1 instruction. 1010 * 1011 * This branch could be a COP1 branch, but in that case we 1012 * would have had a trap for that instruction, and would not 1013 * come through this route. 1014 * 1015 * Linux MIPS branch emulator operates on context, updating the 1016 * cp0_epc. 1017 */ 1018 ir = dec_insn.next_insn; /* process delay slot instr */ 1019 pc_inc = dec_insn.next_pc_inc; 1020 } else { 1021 ir = dec_insn.insn; /* process current instr */ 1022 pc_inc = dec_insn.pc_inc; 1023 } 1024 1025 /* 1026 * Since microMIPS FPU instructios are a subset of MIPS32 FPU 1027 * instructions, we want to convert microMIPS FPU instructions 1028 * into MIPS32 instructions so that we could reuse all of the 1029 * FPU emulation code. 1030 * 1031 * NOTE: We cannot do this for branch instructions since they 1032 * are not a subset. Example: Cannot emulate a 16-bit 1033 * aligned target address with a MIPS32 instruction. 1034 */ 1035 if (dec_insn.micro_mips_mode) { 1036 /* 1037 * If next instruction is a 16-bit instruction, then it 1038 * it cannot be a FPU instruction. This could happen 1039 * since we can be called for non-FPU instructions. 1040 */ 1041 if ((pc_inc == 2) || 1042 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) 1043 == SIGILL)) 1044 return SIGILL; 1045 } 1046 1047emul: 1048 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); 1049 MIPS_FPU_EMU_INC_STATS(emulated); 1050 switch (MIPSInst_OPCODE(ir)) { 1051 case ldc1_op: 1052 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1053 MIPSInst_SIMM(ir)); 1054 MIPS_FPU_EMU_INC_STATS(loads); 1055 1056 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) { 1057 MIPS_FPU_EMU_INC_STATS(errors); 1058 *fault_addr = dva; 1059 return SIGBUS; 1060 } 1061 if (__get_user(dval, dva)) { 1062 MIPS_FPU_EMU_INC_STATS(errors); 1063 *fault_addr = dva; 1064 return SIGSEGV; 1065 } 1066 DITOREG(dval, MIPSInst_RT(ir)); 1067 break; 1068 1069 case sdc1_op: 1070 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1071 MIPSInst_SIMM(ir)); 1072 MIPS_FPU_EMU_INC_STATS(stores); 1073 DIFROMREG(dval, MIPSInst_RT(ir)); 1074 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) { 1075 MIPS_FPU_EMU_INC_STATS(errors); 1076 *fault_addr = dva; 1077 return SIGBUS; 1078 } 1079 if (__put_user(dval, dva)) { 1080 MIPS_FPU_EMU_INC_STATS(errors); 1081 *fault_addr = dva; 1082 return SIGSEGV; 1083 } 1084 break; 1085 1086 case lwc1_op: 1087 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1088 MIPSInst_SIMM(ir)); 1089 MIPS_FPU_EMU_INC_STATS(loads); 1090 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) { 1091 MIPS_FPU_EMU_INC_STATS(errors); 1092 *fault_addr = wva; 1093 return SIGBUS; 1094 } 1095 if (__get_user(wval, wva)) { 1096 MIPS_FPU_EMU_INC_STATS(errors); 1097 *fault_addr = wva; 1098 return SIGSEGV; 1099 } 1100 SITOREG(wval, MIPSInst_RT(ir)); 1101 break; 1102 1103 case swc1_op: 1104 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1105 MIPSInst_SIMM(ir)); 1106 MIPS_FPU_EMU_INC_STATS(stores); 1107 SIFROMREG(wval, MIPSInst_RT(ir)); 1108 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) { 1109 MIPS_FPU_EMU_INC_STATS(errors); 1110 *fault_addr = wva; 1111 return SIGBUS; 1112 } 1113 if (__put_user(wval, wva)) { 1114 MIPS_FPU_EMU_INC_STATS(errors); 1115 *fault_addr = wva; 1116 return SIGSEGV; 1117 } 1118 break; 1119 1120 case cop1_op: 1121 switch (MIPSInst_RS(ir)) { 1122 case dmfc_op: 1123 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1124 return SIGILL; 1125 1126 /* copregister fs -> gpr[rt] */ 1127 if (MIPSInst_RT(ir) != 0) { 1128 DIFROMREG(xcp->regs[MIPSInst_RT(ir)], 1129 MIPSInst_RD(ir)); 1130 } 1131 break; 1132 1133 case dmtc_op: 1134 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1135 return SIGILL; 1136 1137 /* copregister fs <- rt */ 1138 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1139 break; 1140 1141 case mfhc_op: 1142 if (!cpu_has_mips_r2_r6) 1143 goto sigill; 1144 1145 /* copregister rd -> gpr[rt] */ 1146 if (MIPSInst_RT(ir) != 0) { 1147 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], 1148 MIPSInst_RD(ir)); 1149 } 1150 break; 1151 1152 case mthc_op: 1153 if (!cpu_has_mips_r2_r6) 1154 goto sigill; 1155 1156 /* copregister rd <- gpr[rt] */ 1157 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1158 break; 1159 1160 case mfc_op: 1161 /* copregister rd -> gpr[rt] */ 1162 if (MIPSInst_RT(ir) != 0) { 1163 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], 1164 MIPSInst_RD(ir)); 1165 } 1166 break; 1167 1168 case mtc_op: 1169 /* copregister rd <- rt */ 1170 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1171 break; 1172 1173 case cfc_op: 1174 /* cop control register rd -> gpr[rt] */ 1175 cop1_cfc(xcp, ctx, ir); 1176 break; 1177 1178 case ctc_op: 1179 /* copregister rd <- rt */ 1180 cop1_ctc(xcp, ctx, ir); 1181 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1182 return SIGFPE; 1183 } 1184 break; 1185 1186 case bc1eqz_op: 1187 case bc1nez_op: 1188 if (!cpu_has_mips_r6 || delay_slot(xcp)) 1189 return SIGILL; 1190 1191 cond = likely = 0; 1192 switch (MIPSInst_RS(ir)) { 1193 case bc1eqz_op: 1194 if (get_fpr32(¤t->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1) 1195 cond = 1; 1196 break; 1197 case bc1nez_op: 1198 if (!(get_fpr32(¤t->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1)) 1199 cond = 1; 1200 break; 1201 } 1202 goto branch_common; 1203 1204 case bc_op: 1205 if (delay_slot(xcp)) 1206 return SIGILL; 1207 1208 if (cpu_has_mips_4_5_r) 1209 cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; 1210 else 1211 cbit = FPU_CSR_COND; 1212 cond = ctx->fcr31 & cbit; 1213 1214 likely = 0; 1215 switch (MIPSInst_RT(ir) & 3) { 1216 case bcfl_op: 1217 if (cpu_has_mips_2_3_4_5_r) 1218 likely = 1; 1219 /* Fall through */ 1220 case bcf_op: 1221 cond = !cond; 1222 break; 1223 case bctl_op: 1224 if (cpu_has_mips_2_3_4_5_r) 1225 likely = 1; 1226 /* Fall through */ 1227 case bct_op: 1228 break; 1229 } 1230branch_common: 1231 set_delay_slot(xcp); 1232 if (cond) { 1233 /* 1234 * Branch taken: emulate dslot instruction 1235 */ 1236 unsigned long bcpc; 1237 1238 /* 1239 * Remember EPC at the branch to point back 1240 * at so that any delay-slot instruction 1241 * signal is not silently ignored. 1242 */ 1243 bcpc = xcp->cp0_epc; 1244 xcp->cp0_epc += dec_insn.pc_inc; 1245 1246 contpc = MIPSInst_SIMM(ir); 1247 ir = dec_insn.next_insn; 1248 if (dec_insn.micro_mips_mode) { 1249 contpc = (xcp->cp0_epc + (contpc << 1)); 1250 1251 /* If 16-bit instruction, not FPU. */ 1252 if ((dec_insn.next_pc_inc == 2) || 1253 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { 1254 1255 /* 1256 * Since this instruction will 1257 * be put on the stack with 1258 * 32-bit words, get around 1259 * this problem by putting a 1260 * NOP16 as the second one. 1261 */ 1262 if (dec_insn.next_pc_inc == 2) 1263 ir = (ir & (~0xffff)) | MM_NOP16; 1264 1265 /* 1266 * Single step the non-CP1 1267 * instruction in the dslot. 1268 */ 1269 sig = mips_dsemul(xcp, ir, 1270 contpc); 1271 if (sig) 1272 xcp->cp0_epc = bcpc; 1273 /* 1274 * SIGILL forces out of 1275 * the emulation loop. 1276 */ 1277 return sig ? sig : SIGILL; 1278 } 1279 } else 1280 contpc = (xcp->cp0_epc + (contpc << 2)); 1281 1282 switch (MIPSInst_OPCODE(ir)) { 1283 case lwc1_op: 1284 case swc1_op: 1285 goto emul; 1286 1287 case ldc1_op: 1288 case sdc1_op: 1289 if (cpu_has_mips_2_3_4_5_r) 1290 goto emul; 1291 1292 goto bc_sigill; 1293 1294 case cop1_op: 1295 goto emul; 1296 1297 case cop1x_op: 1298 if (cpu_has_mips_4_5_64_r2_r6) 1299 /* its one of ours */ 1300 goto emul; 1301 1302 goto bc_sigill; 1303 1304 case spec_op: 1305 switch (MIPSInst_FUNC(ir)) { 1306 case movc_op: 1307 if (cpu_has_mips_4_5_r) 1308 goto emul; 1309 1310 goto bc_sigill; 1311 } 1312 break; 1313 1314 bc_sigill: 1315 xcp->cp0_epc = bcpc; 1316 return SIGILL; 1317 } 1318 1319 /* 1320 * Single step the non-cp1 1321 * instruction in the dslot 1322 */ 1323 sig = mips_dsemul(xcp, ir, contpc); 1324 if (sig) 1325 xcp->cp0_epc = bcpc; 1326 /* SIGILL forces out of the emulation loop. */ 1327 return sig ? sig : SIGILL; 1328 } else if (likely) { /* branch not taken */ 1329 /* 1330 * branch likely nullifies 1331 * dslot if not taken 1332 */ 1333 xcp->cp0_epc += dec_insn.pc_inc; 1334 contpc += dec_insn.pc_inc; 1335 /* 1336 * else continue & execute 1337 * dslot as normal insn 1338 */ 1339 } 1340 break; 1341 1342 default: 1343 if (!(MIPSInst_RS(ir) & 0x10)) 1344 return SIGILL; 1345 1346 /* a real fpu computation instruction */ 1347 if ((sig = fpu_emu(xcp, ctx, ir))) 1348 return sig; 1349 } 1350 break; 1351 1352 case cop1x_op: 1353 if (!cpu_has_mips_4_5_64_r2_r6) 1354 return SIGILL; 1355 1356 sig = fpux_emu(xcp, ctx, ir, fault_addr); 1357 if (sig) 1358 return sig; 1359 break; 1360 1361 case spec_op: 1362 if (!cpu_has_mips_4_5_r) 1363 return SIGILL; 1364 1365 if (MIPSInst_FUNC(ir) != movc_op) 1366 return SIGILL; 1367 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 1368 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) 1369 xcp->regs[MIPSInst_RD(ir)] = 1370 xcp->regs[MIPSInst_RS(ir)]; 1371 break; 1372 default: 1373sigill: 1374 return SIGILL; 1375 } 1376 1377 /* we did it !! */ 1378 xcp->cp0_epc = contpc; 1379 clear_delay_slot(xcp); 1380 1381 return 0; 1382} 1383 1384/* 1385 * Conversion table from MIPS compare ops 48-63 1386 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); 1387 */ 1388static const unsigned char cmptab[8] = { 1389 0, /* cmp_0 (sig) cmp_sf */ 1390 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ 1391 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ 1392 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ 1393 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ 1394 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ 1395 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ 1396 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ 1397}; 1398 1399 1400/* 1401 * Additional MIPS4 instructions 1402 */ 1403 1404#define DEF3OP(name, p, f1, f2, f3) \ 1405static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \ 1406 union ieee754##p s, union ieee754##p t) \ 1407{ \ 1408 struct _ieee754_csr ieee754_csr_save; \ 1409 s = f1(s, t); \ 1410 ieee754_csr_save = ieee754_csr; \ 1411 s = f2(s, r); \ 1412 ieee754_csr_save.cx |= ieee754_csr.cx; \ 1413 ieee754_csr_save.sx |= ieee754_csr.sx; \ 1414 s = f3(s); \ 1415 ieee754_csr.cx |= ieee754_csr_save.cx; \ 1416 ieee754_csr.sx |= ieee754_csr_save.sx; \ 1417 return s; \ 1418} 1419 1420static union ieee754dp fpemu_dp_recip(union ieee754dp d) 1421{ 1422 return ieee754dp_div(ieee754dp_one(0), d); 1423} 1424 1425static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d) 1426{ 1427 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); 1428} 1429 1430static union ieee754sp fpemu_sp_recip(union ieee754sp s) 1431{ 1432 return ieee754sp_div(ieee754sp_one(0), s); 1433} 1434 1435static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s) 1436{ 1437 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); 1438} 1439 1440DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); 1441DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); 1442DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); 1443DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); 1444DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); 1445DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); 1446DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); 1447DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 1448 1449static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1450 mips_instruction ir, void *__user *fault_addr) 1451{ 1452 unsigned rcsr = 0; /* resulting csr */ 1453 1454 MIPS_FPU_EMU_INC_STATS(cp1xops); 1455 1456 switch (MIPSInst_FMA_FFMT(ir)) { 1457 case s_fmt:{ /* 0 */ 1458 1459 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp); 1460 union ieee754sp fd, fr, fs, ft; 1461 u32 __user *va; 1462 u32 val; 1463 1464 switch (MIPSInst_FUNC(ir)) { 1465 case lwxc1_op: 1466 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1467 xcp->regs[MIPSInst_FT(ir)]); 1468 1469 MIPS_FPU_EMU_INC_STATS(loads); 1470 if (!access_ok(VERIFY_READ, va, sizeof(u32))) { 1471 MIPS_FPU_EMU_INC_STATS(errors); 1472 *fault_addr = va; 1473 return SIGBUS; 1474 } 1475 if (__get_user(val, va)) { 1476 MIPS_FPU_EMU_INC_STATS(errors); 1477 *fault_addr = va; 1478 return SIGSEGV; 1479 } 1480 SITOREG(val, MIPSInst_FD(ir)); 1481 break; 1482 1483 case swxc1_op: 1484 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1485 xcp->regs[MIPSInst_FT(ir)]); 1486 1487 MIPS_FPU_EMU_INC_STATS(stores); 1488 1489 SIFROMREG(val, MIPSInst_FS(ir)); 1490 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { 1491 MIPS_FPU_EMU_INC_STATS(errors); 1492 *fault_addr = va; 1493 return SIGBUS; 1494 } 1495 if (put_user(val, va)) { 1496 MIPS_FPU_EMU_INC_STATS(errors); 1497 *fault_addr = va; 1498 return SIGSEGV; 1499 } 1500 break; 1501 1502 case madd_s_op: 1503 handler = fpemu_sp_madd; 1504 goto scoptop; 1505 case msub_s_op: 1506 handler = fpemu_sp_msub; 1507 goto scoptop; 1508 case nmadd_s_op: 1509 handler = fpemu_sp_nmadd; 1510 goto scoptop; 1511 case nmsub_s_op: 1512 handler = fpemu_sp_nmsub; 1513 goto scoptop; 1514 1515 scoptop: 1516 SPFROMREG(fr, MIPSInst_FR(ir)); 1517 SPFROMREG(fs, MIPSInst_FS(ir)); 1518 SPFROMREG(ft, MIPSInst_FT(ir)); 1519 fd = (*handler) (fr, fs, ft); 1520 SPTOREG(fd, MIPSInst_FD(ir)); 1521 1522 copcsr: 1523 if (ieee754_cxtest(IEEE754_INEXACT)) { 1524 MIPS_FPU_EMU_INC_STATS(ieee754_inexact); 1525 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1526 } 1527 if (ieee754_cxtest(IEEE754_UNDERFLOW)) { 1528 MIPS_FPU_EMU_INC_STATS(ieee754_underflow); 1529 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1530 } 1531 if (ieee754_cxtest(IEEE754_OVERFLOW)) { 1532 MIPS_FPU_EMU_INC_STATS(ieee754_overflow); 1533 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1534 } 1535 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { 1536 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); 1537 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1538 } 1539 1540 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 1541 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1542 /*printk ("SIGFPE: FPU csr = %08x\n", 1543 ctx->fcr31); */ 1544 return SIGFPE; 1545 } 1546 1547 break; 1548 1549 default: 1550 return SIGILL; 1551 } 1552 break; 1553 } 1554 1555 case d_fmt:{ /* 1 */ 1556 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp); 1557 union ieee754dp fd, fr, fs, ft; 1558 u64 __user *va; 1559 u64 val; 1560 1561 switch (MIPSInst_FUNC(ir)) { 1562 case ldxc1_op: 1563 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1564 xcp->regs[MIPSInst_FT(ir)]); 1565 1566 MIPS_FPU_EMU_INC_STATS(loads); 1567 if (!access_ok(VERIFY_READ, va, sizeof(u64))) { 1568 MIPS_FPU_EMU_INC_STATS(errors); 1569 *fault_addr = va; 1570 return SIGBUS; 1571 } 1572 if (__get_user(val, va)) { 1573 MIPS_FPU_EMU_INC_STATS(errors); 1574 *fault_addr = va; 1575 return SIGSEGV; 1576 } 1577 DITOREG(val, MIPSInst_FD(ir)); 1578 break; 1579 1580 case sdxc1_op: 1581 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1582 xcp->regs[MIPSInst_FT(ir)]); 1583 1584 MIPS_FPU_EMU_INC_STATS(stores); 1585 DIFROMREG(val, MIPSInst_FS(ir)); 1586 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { 1587 MIPS_FPU_EMU_INC_STATS(errors); 1588 *fault_addr = va; 1589 return SIGBUS; 1590 } 1591 if (__put_user(val, va)) { 1592 MIPS_FPU_EMU_INC_STATS(errors); 1593 *fault_addr = va; 1594 return SIGSEGV; 1595 } 1596 break; 1597 1598 case madd_d_op: 1599 handler = fpemu_dp_madd; 1600 goto dcoptop; 1601 case msub_d_op: 1602 handler = fpemu_dp_msub; 1603 goto dcoptop; 1604 case nmadd_d_op: 1605 handler = fpemu_dp_nmadd; 1606 goto dcoptop; 1607 case nmsub_d_op: 1608 handler = fpemu_dp_nmsub; 1609 goto dcoptop; 1610 1611 dcoptop: 1612 DPFROMREG(fr, MIPSInst_FR(ir)); 1613 DPFROMREG(fs, MIPSInst_FS(ir)); 1614 DPFROMREG(ft, MIPSInst_FT(ir)); 1615 fd = (*handler) (fr, fs, ft); 1616 DPTOREG(fd, MIPSInst_FD(ir)); 1617 goto copcsr; 1618 1619 default: 1620 return SIGILL; 1621 } 1622 break; 1623 } 1624 1625 case 0x3: 1626 if (MIPSInst_FUNC(ir) != pfetch_op) 1627 return SIGILL; 1628 1629 /* ignore prefx operation */ 1630 break; 1631 1632 default: 1633 return SIGILL; 1634 } 1635 1636 return 0; 1637} 1638 1639 1640 1641/* 1642 * Emulate a single COP1 arithmetic instruction. 1643 */ 1644static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1645 mips_instruction ir) 1646{ 1647 int rfmt; /* resulting format */ 1648 unsigned rcsr = 0; /* resulting csr */ 1649 unsigned int oldrm; 1650 unsigned int cbit; 1651 unsigned cond; 1652 union { 1653 union ieee754dp d; 1654 union ieee754sp s; 1655 int w; 1656 s64 l; 1657 } rv; /* resulting value */ 1658 u64 bits; 1659 1660 MIPS_FPU_EMU_INC_STATS(cp1ops); 1661 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { 1662 case s_fmt: { /* 0 */ 1663 union { 1664 union ieee754sp(*b) (union ieee754sp, union ieee754sp); 1665 union ieee754sp(*u) (union ieee754sp); 1666 } handler; 1667 union ieee754sp fs, ft; 1668 1669 switch (MIPSInst_FUNC(ir)) { 1670 /* binary ops */ 1671 case fadd_op: 1672 handler.b = ieee754sp_add; 1673 goto scopbop; 1674 case fsub_op: 1675 handler.b = ieee754sp_sub; 1676 goto scopbop; 1677 case fmul_op: 1678 handler.b = ieee754sp_mul; 1679 goto scopbop; 1680 case fdiv_op: 1681 handler.b = ieee754sp_div; 1682 goto scopbop; 1683 1684 /* unary ops */ 1685 case fsqrt_op: 1686 if (!cpu_has_mips_2_3_4_5_r) 1687 return SIGILL; 1688 1689 handler.u = ieee754sp_sqrt; 1690 goto scopuop; 1691 1692 /* 1693 * Note that on some MIPS IV implementations such as the 1694 * R5000 and R8000 the FSQRT and FRECIP instructions do not 1695 * achieve full IEEE-754 accuracy - however this emulator does. 1696 */ 1697 case frsqrt_op: 1698 if (!cpu_has_mips_4_5_64_r2_r6) 1699 return SIGILL; 1700 1701 handler.u = fpemu_sp_rsqrt; 1702 goto scopuop; 1703 1704 case frecip_op: 1705 if (!cpu_has_mips_4_5_64_r2_r6) 1706 return SIGILL; 1707 1708 handler.u = fpemu_sp_recip; 1709 goto scopuop; 1710 1711 case fmovc_op: 1712 if (!cpu_has_mips_4_5_r) 1713 return SIGILL; 1714 1715 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 1716 if (((ctx->fcr31 & cond) != 0) != 1717 ((MIPSInst_FT(ir) & 1) != 0)) 1718 return 0; 1719 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1720 break; 1721 1722 case fmovz_op: 1723 if (!cpu_has_mips_4_5_r) 1724 return SIGILL; 1725 1726 if (xcp->regs[MIPSInst_FT(ir)] != 0) 1727 return 0; 1728 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1729 break; 1730 1731 case fmovn_op: 1732 if (!cpu_has_mips_4_5_r) 1733 return SIGILL; 1734 1735 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1736 return 0; 1737 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1738 break; 1739 1740 case fabs_op: 1741 handler.u = ieee754sp_abs; 1742 goto scopuop; 1743 1744 case fneg_op: 1745 handler.u = ieee754sp_neg; 1746 goto scopuop; 1747 1748 case fmov_op: 1749 /* an easy one */ 1750 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1751 goto copcsr; 1752 1753 /* binary op on handler */ 1754scopbop: 1755 SPFROMREG(fs, MIPSInst_FS(ir)); 1756 SPFROMREG(ft, MIPSInst_FT(ir)); 1757 1758 rv.s = (*handler.b) (fs, ft); 1759 goto copcsr; 1760scopuop: 1761 SPFROMREG(fs, MIPSInst_FS(ir)); 1762 rv.s = (*handler.u) (fs); 1763 goto copcsr; 1764copcsr: 1765 if (ieee754_cxtest(IEEE754_INEXACT)) { 1766 MIPS_FPU_EMU_INC_STATS(ieee754_inexact); 1767 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1768 } 1769 if (ieee754_cxtest(IEEE754_UNDERFLOW)) { 1770 MIPS_FPU_EMU_INC_STATS(ieee754_underflow); 1771 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1772 } 1773 if (ieee754_cxtest(IEEE754_OVERFLOW)) { 1774 MIPS_FPU_EMU_INC_STATS(ieee754_overflow); 1775 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1776 } 1777 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) { 1778 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv); 1779 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; 1780 } 1781 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) { 1782 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop); 1783 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1784 } 1785 break; 1786 1787 /* unary conv ops */ 1788 case fcvts_op: 1789 return SIGILL; /* not defined */ 1790 1791 case fcvtd_op: 1792 SPFROMREG(fs, MIPSInst_FS(ir)); 1793 rv.d = ieee754dp_fsp(fs); 1794 rfmt = d_fmt; 1795 goto copcsr; 1796 1797 case fcvtw_op: 1798 SPFROMREG(fs, MIPSInst_FS(ir)); 1799 rv.w = ieee754sp_tint(fs); 1800 rfmt = w_fmt; 1801 goto copcsr; 1802 1803 case fround_op: 1804 case ftrunc_op: 1805 case fceil_op: 1806 case ffloor_op: 1807 if (!cpu_has_mips_2_3_4_5_r) 1808 return SIGILL; 1809 1810 oldrm = ieee754_csr.rm; 1811 SPFROMREG(fs, MIPSInst_FS(ir)); 1812 ieee754_csr.rm = MIPSInst_FUNC(ir); 1813 rv.w = ieee754sp_tint(fs); 1814 ieee754_csr.rm = oldrm; 1815 rfmt = w_fmt; 1816 goto copcsr; 1817 1818 case fcvtl_op: 1819 if (!cpu_has_mips_3_4_5_64_r2_r6) 1820 return SIGILL; 1821 1822 SPFROMREG(fs, MIPSInst_FS(ir)); 1823 rv.l = ieee754sp_tlong(fs); 1824 rfmt = l_fmt; 1825 goto copcsr; 1826 1827 case froundl_op: 1828 case ftruncl_op: 1829 case fceill_op: 1830 case ffloorl_op: 1831 if (!cpu_has_mips_3_4_5_64_r2_r6) 1832 return SIGILL; 1833 1834 oldrm = ieee754_csr.rm; 1835 SPFROMREG(fs, MIPSInst_FS(ir)); 1836 ieee754_csr.rm = MIPSInst_FUNC(ir); 1837 rv.l = ieee754sp_tlong(fs); 1838 ieee754_csr.rm = oldrm; 1839 rfmt = l_fmt; 1840 goto copcsr; 1841 1842 default: 1843 if (MIPSInst_FUNC(ir) >= fcmp_op) { 1844 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 1845 union ieee754sp fs, ft; 1846 1847 SPFROMREG(fs, MIPSInst_FS(ir)); 1848 SPFROMREG(ft, MIPSInst_FT(ir)); 1849 rv.w = ieee754sp_cmp(fs, ft, 1850 cmptab[cmpop & 0x7], cmpop & 0x8); 1851 rfmt = -1; 1852 if ((cmpop & 0x8) && ieee754_cxtest 1853 (IEEE754_INVALID_OPERATION)) 1854 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 1855 else 1856 goto copcsr; 1857 1858 } else 1859 return SIGILL; 1860 break; 1861 } 1862 break; 1863 } 1864 1865 case d_fmt: { 1866 union ieee754dp fs, ft; 1867 union { 1868 union ieee754dp(*b) (union ieee754dp, union ieee754dp); 1869 union ieee754dp(*u) (union ieee754dp); 1870 } handler; 1871 1872 switch (MIPSInst_FUNC(ir)) { 1873 /* binary ops */ 1874 case fadd_op: 1875 handler.b = ieee754dp_add; 1876 goto dcopbop; 1877 case fsub_op: 1878 handler.b = ieee754dp_sub; 1879 goto dcopbop; 1880 case fmul_op: 1881 handler.b = ieee754dp_mul; 1882 goto dcopbop; 1883 case fdiv_op: 1884 handler.b = ieee754dp_div; 1885 goto dcopbop; 1886 1887 /* unary ops */ 1888 case fsqrt_op: 1889 if (!cpu_has_mips_2_3_4_5_r) 1890 return SIGILL; 1891 1892 handler.u = ieee754dp_sqrt; 1893 goto dcopuop; 1894 /* 1895 * Note that on some MIPS IV implementations such as the 1896 * R5000 and R8000 the FSQRT and FRECIP instructions do not 1897 * achieve full IEEE-754 accuracy - however this emulator does. 1898 */ 1899 case frsqrt_op: 1900 if (!cpu_has_mips_4_5_64_r2_r6) 1901 return SIGILL; 1902 1903 handler.u = fpemu_dp_rsqrt; 1904 goto dcopuop; 1905 case frecip_op: 1906 if (!cpu_has_mips_4_5_64_r2_r6) 1907 return SIGILL; 1908 1909 handler.u = fpemu_dp_recip; 1910 goto dcopuop; 1911 case fmovc_op: 1912 if (!cpu_has_mips_4_5_r) 1913 return SIGILL; 1914 1915 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 1916 if (((ctx->fcr31 & cond) != 0) != 1917 ((MIPSInst_FT(ir) & 1) != 0)) 1918 return 0; 1919 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1920 break; 1921 case fmovz_op: 1922 if (!cpu_has_mips_4_5_r) 1923 return SIGILL; 1924 1925 if (xcp->regs[MIPSInst_FT(ir)] != 0) 1926 return 0; 1927 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1928 break; 1929 case fmovn_op: 1930 if (!cpu_has_mips_4_5_r) 1931 return SIGILL; 1932 1933 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1934 return 0; 1935 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1936 break; 1937 case fabs_op: 1938 handler.u = ieee754dp_abs; 1939 goto dcopuop; 1940 1941 case fneg_op: 1942 handler.u = ieee754dp_neg; 1943 goto dcopuop; 1944 1945 case fmov_op: 1946 /* an easy one */ 1947 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1948 goto copcsr; 1949 1950 /* binary op on handler */ 1951dcopbop: 1952 DPFROMREG(fs, MIPSInst_FS(ir)); 1953 DPFROMREG(ft, MIPSInst_FT(ir)); 1954 1955 rv.d = (*handler.b) (fs, ft); 1956 goto copcsr; 1957dcopuop: 1958 DPFROMREG(fs, MIPSInst_FS(ir)); 1959 rv.d = (*handler.u) (fs); 1960 goto copcsr; 1961 1962 /* 1963 * unary conv ops 1964 */ 1965 case fcvts_op: 1966 DPFROMREG(fs, MIPSInst_FS(ir)); 1967 rv.s = ieee754sp_fdp(fs); 1968 rfmt = s_fmt; 1969 goto copcsr; 1970 1971 case fcvtd_op: 1972 return SIGILL; /* not defined */ 1973 1974 case fcvtw_op: 1975 DPFROMREG(fs, MIPSInst_FS(ir)); 1976 rv.w = ieee754dp_tint(fs); /* wrong */ 1977 rfmt = w_fmt; 1978 goto copcsr; 1979 1980 case fround_op: 1981 case ftrunc_op: 1982 case fceil_op: 1983 case ffloor_op: 1984 if (!cpu_has_mips_2_3_4_5_r) 1985 return SIGILL; 1986 1987 oldrm = ieee754_csr.rm; 1988 DPFROMREG(fs, MIPSInst_FS(ir)); 1989 ieee754_csr.rm = MIPSInst_FUNC(ir); 1990 rv.w = ieee754dp_tint(fs); 1991 ieee754_csr.rm = oldrm; 1992 rfmt = w_fmt; 1993 goto copcsr; 1994 1995 case fcvtl_op: 1996 if (!cpu_has_mips_3_4_5_64_r2_r6) 1997 return SIGILL; 1998 1999 DPFROMREG(fs, MIPSInst_FS(ir)); 2000 rv.l = ieee754dp_tlong(fs); 2001 rfmt = l_fmt; 2002 goto copcsr; 2003 2004 case froundl_op: 2005 case ftruncl_op: 2006 case fceill_op: 2007 case ffloorl_op: 2008 if (!cpu_has_mips_3_4_5_64_r2_r6) 2009 return SIGILL; 2010 2011 oldrm = ieee754_csr.rm; 2012 DPFROMREG(fs, MIPSInst_FS(ir)); 2013 ieee754_csr.rm = MIPSInst_FUNC(ir); 2014 rv.l = ieee754dp_tlong(fs); 2015 ieee754_csr.rm = oldrm; 2016 rfmt = l_fmt; 2017 goto copcsr; 2018 2019 default: 2020 if (MIPSInst_FUNC(ir) >= fcmp_op) { 2021 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 2022 union ieee754dp fs, ft; 2023 2024 DPFROMREG(fs, MIPSInst_FS(ir)); 2025 DPFROMREG(ft, MIPSInst_FT(ir)); 2026 rv.w = ieee754dp_cmp(fs, ft, 2027 cmptab[cmpop & 0x7], cmpop & 0x8); 2028 rfmt = -1; 2029 if ((cmpop & 0x8) 2030 && 2031 ieee754_cxtest 2032 (IEEE754_INVALID_OPERATION)) 2033 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 2034 else 2035 goto copcsr; 2036 2037 } 2038 else { 2039 return SIGILL; 2040 } 2041 break; 2042 } 2043 break; 2044 2045 case w_fmt: 2046 switch (MIPSInst_FUNC(ir)) { 2047 case fcvts_op: 2048 /* convert word to single precision real */ 2049 SPFROMREG(fs, MIPSInst_FS(ir)); 2050 rv.s = ieee754sp_fint(fs.bits); 2051 rfmt = s_fmt; 2052 goto copcsr; 2053 case fcvtd_op: 2054 /* convert word to double precision real */ 2055 SPFROMREG(fs, MIPSInst_FS(ir)); 2056 rv.d = ieee754dp_fint(fs.bits); 2057 rfmt = d_fmt; 2058 goto copcsr; 2059 default: 2060 return SIGILL; 2061 } 2062 break; 2063 } 2064 2065 case l_fmt: 2066 2067 if (!cpu_has_mips_3_4_5_64_r2_r6) 2068 return SIGILL; 2069 2070 DIFROMREG(bits, MIPSInst_FS(ir)); 2071 2072 switch (MIPSInst_FUNC(ir)) { 2073 case fcvts_op: 2074 /* convert long to single precision real */ 2075 rv.s = ieee754sp_flong(bits); 2076 rfmt = s_fmt; 2077 goto copcsr; 2078 case fcvtd_op: 2079 /* convert long to double precision real */ 2080 rv.d = ieee754dp_flong(bits); 2081 rfmt = d_fmt; 2082 goto copcsr; 2083 default: 2084 return SIGILL; 2085 } 2086 break; 2087 2088 default: 2089 return SIGILL; 2090 } 2091 2092 /* 2093 * Update the fpu CSR register for this operation. 2094 * If an exception is required, generate a tidy SIGFPE exception, 2095 * without updating the result register. 2096 * Note: cause exception bits do not accumulate, they are rewritten 2097 * for each op; only the flag/sticky bits accumulate. 2098 */ 2099 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 2100 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 2101 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */ 2102 return SIGFPE; 2103 } 2104 2105 /* 2106 * Now we can safely write the result back to the register file. 2107 */ 2108 switch (rfmt) { 2109 case -1: 2110 2111 if (cpu_has_mips_4_5_r) 2112 cbit = fpucondbit[MIPSInst_FD(ir) >> 2]; 2113 else 2114 cbit = FPU_CSR_COND; 2115 if (rv.w) 2116 ctx->fcr31 |= cbit; 2117 else 2118 ctx->fcr31 &= ~cbit; 2119 break; 2120 2121 case d_fmt: 2122 DPTOREG(rv.d, MIPSInst_FD(ir)); 2123 break; 2124 case s_fmt: 2125 SPTOREG(rv.s, MIPSInst_FD(ir)); 2126 break; 2127 case w_fmt: 2128 SITOREG(rv.w, MIPSInst_FD(ir)); 2129 break; 2130 case l_fmt: 2131 if (!cpu_has_mips_3_4_5_64_r2_r6) 2132 return SIGILL; 2133 2134 DITOREG(rv.l, MIPSInst_FD(ir)); 2135 break; 2136 default: 2137 return SIGILL; 2138 } 2139 2140 return 0; 2141} 2142 2143int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 2144 int has_fpu, void *__user *fault_addr) 2145{ 2146 unsigned long oldepc, prevepc; 2147 struct mm_decoded_insn dec_insn; 2148 u16 instr[4]; 2149 u16 *instr_ptr; 2150 int sig = 0; 2151 2152 oldepc = xcp->cp0_epc; 2153 do { 2154 prevepc = xcp->cp0_epc; 2155 2156 if (get_isa16_mode(prevepc) && cpu_has_mmips) { 2157 /* 2158 * Get next 2 microMIPS instructions and convert them 2159 * into 32-bit instructions. 2160 */ 2161 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || 2162 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || 2163 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || 2164 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { 2165 MIPS_FPU_EMU_INC_STATS(errors); 2166 return SIGBUS; 2167 } 2168 instr_ptr = instr; 2169 2170 /* Get first instruction. */ 2171 if (mm_insn_16bit(*instr_ptr)) { 2172 /* Duplicate the half-word. */ 2173 dec_insn.insn = (*instr_ptr << 16) | 2174 (*instr_ptr); 2175 /* 16-bit instruction. */ 2176 dec_insn.pc_inc = 2; 2177 instr_ptr += 1; 2178 } else { 2179 dec_insn.insn = (*instr_ptr << 16) | 2180 *(instr_ptr+1); 2181 /* 32-bit instruction. */ 2182 dec_insn.pc_inc = 4; 2183 instr_ptr += 2; 2184 } 2185 /* Get second instruction. */ 2186 if (mm_insn_16bit(*instr_ptr)) { 2187 /* Duplicate the half-word. */ 2188 dec_insn.next_insn = (*instr_ptr << 16) | 2189 (*instr_ptr); 2190 /* 16-bit instruction. */ 2191 dec_insn.next_pc_inc = 2; 2192 } else { 2193 dec_insn.next_insn = (*instr_ptr << 16) | 2194 *(instr_ptr+1); 2195 /* 32-bit instruction. */ 2196 dec_insn.next_pc_inc = 4; 2197 } 2198 dec_insn.micro_mips_mode = 1; 2199 } else { 2200 if ((get_user(dec_insn.insn, 2201 (mips_instruction __user *) xcp->cp0_epc)) || 2202 (get_user(dec_insn.next_insn, 2203 (mips_instruction __user *)(xcp->cp0_epc+4)))) { 2204 MIPS_FPU_EMU_INC_STATS(errors); 2205 return SIGBUS; 2206 } 2207 dec_insn.pc_inc = 4; 2208 dec_insn.next_pc_inc = 4; 2209 dec_insn.micro_mips_mode = 0; 2210 } 2211 2212 if ((dec_insn.insn == 0) || 2213 ((dec_insn.pc_inc == 2) && 2214 ((dec_insn.insn & 0xffff) == MM_NOP16))) 2215 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ 2216 else { 2217 /* 2218 * The 'ieee754_csr' is an alias of ctx->fcr31. 2219 * No need to copy ctx->fcr31 to ieee754_csr. 2220 */ 2221 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); 2222 } 2223 2224 if (has_fpu) 2225 break; 2226 if (sig) 2227 break; 2228 2229 cond_resched(); 2230 } while (xcp->cp0_epc > prevepc); 2231 2232 /* SIGILL indicates a non-fpu instruction */ 2233 if (sig == SIGILL && xcp->cp0_epc != oldepc) 2234 /* but if EPC has advanced, then ignore it */ 2235 sig = 0; 2236 2237 return sig; 2238} 2239