1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * Copyright (C) 2001 Ralf Baechle
6 * Copyright (C) 2005  MIPS Technologies, Inc.	All rights reserved.
7 *	Author: Maciej W. Rozycki <macro@mips.com>
8 *
9 * This file define the irq handler for MIPS CPU interrupts.
10 *
11 * This program is free software; you can redistribute	it and/or modify it
12 * under  the terms of	the GNU General	 Public License as published by the
13 * Free Software Foundation;  either version 2 of the  License, or (at your
14 * option) any later version.
15 */
16
17/*
18 * Almost all MIPS CPUs define 8 interrupt sources.  They are typically
19 * level triggered (i.e., cannot be cleared from CPU; must be cleared from
20 * device).  The first two are software interrupts which we don't really
21 * use or support.  The last one is usually the CPU timer interrupt if
22 * counter register is present or, for CPUs with an external FPU, by
23 * convention it's the FPU exception interrupt.
24 *
25 * Don't even think about using this on SMP.  You have been warned.
26 *
27 * This file exports one global function:
28 *	void mips_cpu_irq_init(void);
29 */
30#include <linux/init.h>
31#include <linux/interrupt.h>
32#include <linux/kernel.h>
33#include <linux/irq.h>
34#include <linux/irqdomain.h>
35
36#include <asm/irq_cpu.h>
37#include <asm/mipsregs.h>
38#include <asm/mipsmtregs.h>
39#include <asm/setup.h>
40
41static inline void unmask_mips_irq(struct irq_data *d)
42{
43	set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
44	irq_enable_hazard();
45}
46
47static inline void mask_mips_irq(struct irq_data *d)
48{
49	clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
50	irq_disable_hazard();
51}
52
53static struct irq_chip mips_cpu_irq_controller = {
54	.name		= "MIPS",
55	.irq_ack	= mask_mips_irq,
56	.irq_mask	= mask_mips_irq,
57	.irq_mask_ack	= mask_mips_irq,
58	.irq_unmask	= unmask_mips_irq,
59	.irq_eoi	= unmask_mips_irq,
60	.irq_disable	= mask_mips_irq,
61	.irq_enable	= unmask_mips_irq,
62};
63
64/*
65 * Basically the same as above but taking care of all the MT stuff
66 */
67
68static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
69{
70	unsigned int vpflags = dvpe();
71
72	clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
73	evpe(vpflags);
74	unmask_mips_irq(d);
75	return 0;
76}
77
78/*
79 * While we ack the interrupt interrupts are disabled and thus we don't need
80 * to deal with concurrency issues.  Same for mips_cpu_irq_end.
81 */
82static void mips_mt_cpu_irq_ack(struct irq_data *d)
83{
84	unsigned int vpflags = dvpe();
85	clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
86	evpe(vpflags);
87	mask_mips_irq(d);
88}
89
90static struct irq_chip mips_mt_cpu_irq_controller = {
91	.name		= "MIPS",
92	.irq_startup	= mips_mt_cpu_irq_startup,
93	.irq_ack	= mips_mt_cpu_irq_ack,
94	.irq_mask	= mask_mips_irq,
95	.irq_mask_ack	= mips_mt_cpu_irq_ack,
96	.irq_unmask	= unmask_mips_irq,
97	.irq_eoi	= unmask_mips_irq,
98	.irq_disable	= mask_mips_irq,
99	.irq_enable	= unmask_mips_irq,
100};
101
102asmlinkage void __weak plat_irq_dispatch(void)
103{
104	unsigned long pending = read_c0_cause() & read_c0_status() & ST0_IM;
105	int irq;
106
107	if (!pending) {
108		spurious_interrupt();
109		return;
110	}
111
112	pending >>= CAUSEB_IP;
113	while (pending) {
114		irq = fls(pending) - 1;
115		do_IRQ(MIPS_CPU_IRQ_BASE + irq);
116		pending &= ~BIT(irq);
117	}
118}
119
120static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
121			     irq_hw_number_t hw)
122{
123	static struct irq_chip *chip;
124
125	if (hw < 2 && cpu_has_mipsmt) {
126		/* Software interrupts are used for MT/CMT IPI */
127		chip = &mips_mt_cpu_irq_controller;
128	} else {
129		chip = &mips_cpu_irq_controller;
130	}
131
132	if (cpu_has_vint)
133		set_vi_handler(hw, plat_irq_dispatch);
134
135	irq_set_chip_and_handler(irq, chip, handle_percpu_irq);
136
137	return 0;
138}
139
140static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
141	.map = mips_cpu_intc_map,
142	.xlate = irq_domain_xlate_onecell,
143};
144
145static void __init __mips_cpu_irq_init(struct device_node *of_node)
146{
147	struct irq_domain *domain;
148
149	/* Mask interrupts. */
150	clear_c0_status(ST0_IM);
151	clear_c0_cause(CAUSEF_IP);
152
153	domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
154				       &mips_cpu_intc_irq_domain_ops, NULL);
155	if (!domain)
156		panic("Failed to add irqdomain for MIPS CPU");
157}
158
159void __init mips_cpu_irq_init(void)
160{
161	__mips_cpu_irq_init(NULL);
162}
163
164int __init mips_cpu_irq_of_init(struct device_node *of_node,
165				struct device_node *parent)
166{
167	__mips_cpu_irq_init(of_node);
168	return 0;
169}
170