1 /*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform time support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/time.h>
19
20 #include <linux/clockchips.h>
21 #include <linux/sched_clock.h>
22
23 #include <asm/mach-jz4740/irq.h>
24 #include <asm/mach-jz4740/timer.h>
25 #include <asm/time.h>
26
27 #include "clock.h"
28
29 #define TIMER_CLOCKEVENT 0
30 #define TIMER_CLOCKSOURCE 1
31
32 static uint16_t jz4740_jiffies_per_tick;
33
jz4740_clocksource_read(struct clocksource * cs)34 static cycle_t jz4740_clocksource_read(struct clocksource *cs)
35 {
36 return jz4740_timer_get_count(TIMER_CLOCKSOURCE);
37 }
38
39 static struct clocksource jz4740_clocksource = {
40 .name = "jz4740-timer",
41 .rating = 200,
42 .read = jz4740_clocksource_read,
43 .mask = CLOCKSOURCE_MASK(16),
44 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
45 };
46
jz4740_read_sched_clock(void)47 static u64 notrace jz4740_read_sched_clock(void)
48 {
49 return jz4740_timer_get_count(TIMER_CLOCKSOURCE);
50 }
51
jz4740_clockevent_irq(int irq,void * devid)52 static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
53 {
54 struct clock_event_device *cd = devid;
55
56 jz4740_timer_ack_full(TIMER_CLOCKEVENT);
57
58 if (cd->mode != CLOCK_EVT_MODE_PERIODIC)
59 jz4740_timer_disable(TIMER_CLOCKEVENT);
60
61 cd->event_handler(cd);
62
63 return IRQ_HANDLED;
64 }
65
jz4740_clockevent_set_mode(enum clock_event_mode mode,struct clock_event_device * cd)66 static void jz4740_clockevent_set_mode(enum clock_event_mode mode,
67 struct clock_event_device *cd)
68 {
69 switch (mode) {
70 case CLOCK_EVT_MODE_PERIODIC:
71 jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
72 jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
73 case CLOCK_EVT_MODE_RESUME:
74 jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
75 jz4740_timer_enable(TIMER_CLOCKEVENT);
76 break;
77 case CLOCK_EVT_MODE_ONESHOT:
78 case CLOCK_EVT_MODE_SHUTDOWN:
79 jz4740_timer_disable(TIMER_CLOCKEVENT);
80 break;
81 default:
82 break;
83 }
84 }
85
jz4740_clockevent_set_next(unsigned long evt,struct clock_event_device * cd)86 static int jz4740_clockevent_set_next(unsigned long evt,
87 struct clock_event_device *cd)
88 {
89 jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
90 jz4740_timer_set_period(TIMER_CLOCKEVENT, evt);
91 jz4740_timer_enable(TIMER_CLOCKEVENT);
92
93 return 0;
94 }
95
96 static struct clock_event_device jz4740_clockevent = {
97 .name = "jz4740-timer",
98 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
99 .set_next_event = jz4740_clockevent_set_next,
100 .set_mode = jz4740_clockevent_set_mode,
101 .rating = 200,
102 .irq = JZ4740_IRQ_TCU0,
103 };
104
105 static struct irqaction timer_irqaction = {
106 .handler = jz4740_clockevent_irq,
107 .flags = IRQF_PERCPU | IRQF_TIMER,
108 .name = "jz4740-timerirq",
109 .dev_id = &jz4740_clockevent,
110 };
111
plat_time_init(void)112 void __init plat_time_init(void)
113 {
114 int ret;
115 uint32_t clk_rate;
116 uint16_t ctrl;
117
118 jz4740_timer_init();
119
120 clk_rate = jz4740_clock_bdata.ext_rate >> 4;
121 jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
122
123 clockevent_set_clock(&jz4740_clockevent, clk_rate);
124 jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent);
125 jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent);
126 jz4740_clockevent.cpumask = cpumask_of(0);
127
128 clockevents_register_device(&jz4740_clockevent);
129
130 ret = clocksource_register_hz(&jz4740_clocksource, clk_rate);
131
132 if (ret)
133 printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
134
135 sched_clock_register(jz4740_read_sched_clock, 16, clk_rate);
136
137 setup_irq(JZ4740_IRQ_TCU0, &timer_irqaction);
138
139 ctrl = JZ_TIMER_CTRL_PRESCALE_16 | JZ_TIMER_CTRL_SRC_EXT;
140
141 jz4740_timer_set_ctrl(TIMER_CLOCKEVENT, ctrl);
142 jz4740_timer_set_ctrl(TIMER_CLOCKSOURCE, ctrl);
143
144 jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
145 jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
146
147 jz4740_timer_set_period(TIMER_CLOCKSOURCE, 0xffff);
148
149 jz4740_timer_enable(TIMER_CLOCKEVENT);
150 jz4740_timer_enable(TIMER_CLOCKSOURCE);
151 }
152