1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2009 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28/** 29 * Typedefs and defines for working with Octeon physical addresses. 30 * 31 */ 32#ifndef __CVMX_ADDRESS_H__ 33#define __CVMX_ADDRESS_H__ 34 35#if 0 36typedef enum { 37 CVMX_MIPS_SPACE_XKSEG = 3LL, 38 CVMX_MIPS_SPACE_XKPHYS = 2LL, 39 CVMX_MIPS_SPACE_XSSEG = 1LL, 40 CVMX_MIPS_SPACE_XUSEG = 0LL 41} cvmx_mips_space_t; 42#endif 43 44typedef enum { 45 CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL, 46 CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL, 47 CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL, 48 CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL 49} cvmx_mips_xkseg_space_t; 50 51/* decodes <14:13> of a kseg3 window address */ 52typedef enum { 53 CVMX_ADD_WIN_SCR = 0L, 54 /* see cvmx_add_win_dma_dec_t for further decode */ 55 CVMX_ADD_WIN_DMA = 1L, 56 CVMX_ADD_WIN_UNUSED = 2L, 57 CVMX_ADD_WIN_UNUSED2 = 3L 58} cvmx_add_win_dec_t; 59 60/* decode within DMA space */ 61typedef enum { 62 /* 63 * Add store data to the write buffer entry, allocating it if 64 * necessary. 65 */ 66 CVMX_ADD_WIN_DMA_ADD = 0L, 67 /* send out the write buffer entry to DRAM */ 68 CVMX_ADD_WIN_DMA_SENDMEM = 1L, 69 /* store data must be normal DRAM memory space address in this case */ 70 /* send out the write buffer entry as an IOBDMA command */ 71 CVMX_ADD_WIN_DMA_SENDDMA = 2L, 72 /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */ 73 /* send out the write buffer entry as an IO write */ 74 CVMX_ADD_WIN_DMA_SENDIO = 3L, 75 /* store data must be normal IO space address in this case */ 76 /* send out a single-tick command on the NCB bus */ 77 CVMX_ADD_WIN_DMA_SENDSINGLE = 4L, 78 /* no write buffer data needed/used */ 79} cvmx_add_win_dma_dec_t; 80 81/* 82 * Physical Address Decode 83 * 84 * Octeon-I HW never interprets this X (<39:36> reserved 85 * for future expansion), software should set to 0. 86 * 87 * - 0x0 XXX0 0000 0000 to DRAM Cached 88 * - 0x0 XXX0 0FFF FFFF 89 * 90 * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000 91 * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF) 92 * 93 * - 0x0 XXX0 2000 0000 to DRAM Cached 94 * - 0x0 XXXF FFFF FFFF 95 * 96 * - 0x1 00X0 0000 0000 to Boot Bus Uncached 97 * - 0x1 00XF FFFF FFFF 98 * 99 * - 0x1 01X0 0000 0000 to Other NCB Uncached 100 * - 0x1 FFXF FFFF FFFF devices 101 * 102 * Decode of all Octeon addresses 103 */ 104typedef union { 105 106 uint64_t u64; 107#ifdef __BIG_ENDIAN_BITFIELD 108 /* mapped or unmapped virtual address */ 109 struct { 110 uint64_t R:2; 111 uint64_t offset:62; 112 } sva; 113 114 /* mapped USEG virtual addresses (typically) */ 115 struct { 116 uint64_t zeroes:33; 117 uint64_t offset:31; 118 } suseg; 119 120 /* mapped or unmapped virtual address */ 121 struct { 122 uint64_t ones:33; 123 uint64_t sp:2; 124 uint64_t offset:29; 125 } sxkseg; 126 127 /* 128 * physical address accessed through xkphys unmapped virtual 129 * address. 130 */ 131 struct { 132 uint64_t R:2; /* CVMX_MIPS_SPACE_XKPHYS in this case */ 133 uint64_t cca:3; /* ignored by octeon */ 134 uint64_t mbz:10; 135 uint64_t pa:49; /* physical address */ 136 } sxkphys; 137 138 /* physical address */ 139 struct { 140 uint64_t mbz:15; 141 /* if set, the address is uncached and resides on MCB bus */ 142 uint64_t is_io:1; 143 /* 144 * the hardware ignores this field when is_io==0, else 145 * device ID. 146 */ 147 uint64_t did:8; 148 /* the hardware ignores <39:36> in Octeon I */ 149 uint64_t unaddr:4; 150 uint64_t offset:36; 151 } sphys; 152 153 /* physical mem address */ 154 struct { 155 /* techically, <47:40> are dont-cares */ 156 uint64_t zeroes:24; 157 /* the hardware ignores <39:36> in Octeon I */ 158 uint64_t unaddr:4; 159 uint64_t offset:36; 160 } smem; 161 162 /* physical IO address */ 163 struct { 164 uint64_t mem_region:2; 165 uint64_t mbz:13; 166 /* 1 in this case */ 167 uint64_t is_io:1; 168 /* 169 * The hardware ignores this field when is_io==0, else 170 * device ID. 171 */ 172 uint64_t did:8; 173 /* the hardware ignores <39:36> in Octeon I */ 174 uint64_t unaddr:4; 175 uint64_t offset:36; 176 } sio; 177 178 /* 179 * Scratchpad virtual address - accessed through a window at 180 * the end of kseg3 181 */ 182 struct { 183 uint64_t ones:49; 184 /* CVMX_ADD_WIN_SCR (0) in this case */ 185 cvmx_add_win_dec_t csrdec:2; 186 uint64_t addr:13; 187 } sscr; 188 189 /* there should only be stores to IOBDMA space, no loads */ 190 /* 191 * IOBDMA virtual address - accessed through a window at the 192 * end of kseg3 193 */ 194 struct { 195 uint64_t ones:49; 196 uint64_t csrdec:2; /* CVMX_ADD_WIN_DMA (1) in this case */ 197 uint64_t unused2:3; 198 uint64_t type:3; 199 uint64_t addr:7; 200 } sdma; 201 202 struct { 203 uint64_t didspace:24; 204 uint64_t unused:40; 205 } sfilldidspace; 206#else 207 struct { 208 uint64_t offset:62; 209 uint64_t R:2; 210 } sva; 211 212 struct { 213 uint64_t offset:31; 214 uint64_t zeroes:33; 215 } suseg; 216 217 struct { 218 uint64_t offset:29; 219 uint64_t sp:2; 220 uint64_t ones:33; 221 } sxkseg; 222 223 struct { 224 uint64_t pa:49; 225 uint64_t mbz:10; 226 uint64_t cca:3; 227 uint64_t R:2; 228 } sxkphys; 229 230 struct { 231 uint64_t offset:36; 232 uint64_t unaddr:4; 233 uint64_t did:8; 234 uint64_t is_io:1; 235 uint64_t mbz:15; 236 } sphys; 237 238 struct { 239 uint64_t offset:36; 240 uint64_t unaddr:4; 241 uint64_t zeroes:24; 242 } smem; 243 244 struct { 245 uint64_t offset:36; 246 uint64_t unaddr:4; 247 uint64_t did:8; 248 uint64_t is_io:1; 249 uint64_t mbz:13; 250 uint64_t mem_region:2; 251 } sio; 252 253 struct { 254 uint64_t addr:13; 255 cvmx_add_win_dec_t csrdec:2; 256 uint64_t ones:49; 257 } sscr; 258 259 struct { 260 uint64_t addr:7; 261 uint64_t type:3; 262 uint64_t unused2:3; 263 uint64_t csrdec:2; 264 uint64_t ones:49; 265 } sdma; 266 267 struct { 268 uint64_t unused:40; 269 uint64_t didspace:24; 270 } sfilldidspace; 271#endif 272 273} cvmx_addr_t; 274 275/* These macros for used by 32 bit applications */ 276 277#define CVMX_MIPS32_SPACE_KSEG0 1l 278#define CVMX_ADD_SEG32(segment, add) \ 279 (((int32_t)segment << 31) | (int32_t)(add)) 280 281/* 282 * Currently all IOs are performed using XKPHYS addressing. Linux uses 283 * the CvmMemCtl register to enable XKPHYS addressing to IO space from 284 * user mode. Future OSes may need to change the upper bits of IO 285 * addresses. The following define controls the upper two bits for all 286 * IO addresses generated by the simple executive library. 287 */ 288#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS 289 290/* These macros simplify the process of creating common IO addresses */ 291#define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add)) 292#ifndef CVMX_ADD_IO_SEG 293#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add)) 294#endif 295#define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did)) 296#define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40) 297#define CVMX_FULL_DID(did, subdid) (((did) << 3) | (subdid)) 298 299 /* from include/ncb_rsl_id.v */ 300#define CVMX_OCT_DID_MIS 0ULL /* misc stuff */ 301#define CVMX_OCT_DID_GMX0 1ULL 302#define CVMX_OCT_DID_GMX1 2ULL 303#define CVMX_OCT_DID_PCI 3ULL 304#define CVMX_OCT_DID_KEY 4ULL 305#define CVMX_OCT_DID_FPA 5ULL 306#define CVMX_OCT_DID_DFA 6ULL 307#define CVMX_OCT_DID_ZIP 7ULL 308#define CVMX_OCT_DID_RNG 8ULL 309#define CVMX_OCT_DID_IPD 9ULL 310#define CVMX_OCT_DID_PKT 10ULL 311#define CVMX_OCT_DID_TIM 11ULL 312#define CVMX_OCT_DID_TAG 12ULL 313 /* the rest are not on the IO bus */ 314#define CVMX_OCT_DID_L2C 16ULL 315#define CVMX_OCT_DID_LMC 17ULL 316#define CVMX_OCT_DID_SPX0 18ULL 317#define CVMX_OCT_DID_SPX1 19ULL 318#define CVMX_OCT_DID_PIP 20ULL 319#define CVMX_OCT_DID_ASX0 22ULL 320#define CVMX_OCT_DID_ASX1 23ULL 321#define CVMX_OCT_DID_IOB 30ULL 322 323#define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL) 324#define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL) 325#define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL) 326#define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL) 327#define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL) 328#define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL) 329#define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL) 330#define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL) 331#define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL) 332#define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL) 333#define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL) 334#define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL) 335#define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL) 336#define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL) 337#define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL) 338#define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL) 339#define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL) 340 341#endif /* __CVMX_ADDRESS_H__ */ 342