1/******************************************************************
2 * Copyright (c) 2000-2007 PMC-Sierra INC.
3 *
4 *     This program is free software; you can redistribute it
5 *     and/or modify it under the terms of the GNU General
6 *     Public License as published by the Free Software
7 *     Foundation; either version 2 of the License, or (at your
8 *     option) any later version.
9 *
10 *     This program is distributed in the hope that it will be
11 *     useful, but WITHOUT ANY WARRANTY; without even the implied
12 *     warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 *     PURPOSE.  See the GNU General Public License for more
14 *     details.
15 *
16 *     You should have received a copy of the GNU General Public
17 *     License along with this program; if not, write to the Free
18 *     Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
19 *     02139, USA.
20 *
21 * PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND
22 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS
23 * SOFTWARE.
24 */
25#ifndef MSP_USB_H_
26#define MSP_USB_H_
27
28#define NUM_USB_DEVS   1
29
30/* Register spaces for USB host 0 */
31#define MSP_USB0_MAB_START	(MSP_USB0_BASE + 0x0)
32#define MSP_USB0_MAB_END	(MSP_USB0_BASE + 0x17)
33#define MSP_USB0_ID_START	(MSP_USB0_BASE + 0x40000)
34#define MSP_USB0_ID_END		(MSP_USB0_BASE + 0x4008f)
35#define MSP_USB0_HS_START	(MSP_USB0_BASE + 0x40100)
36#define MSP_USB0_HS_END		(MSP_USB0_BASE + 0x401FF)
37
38/* Register spaces for USB host 1 */
39#define MSP_USB1_MAB_START	(MSP_USB1_BASE + 0x0)
40#define MSP_USB1_MAB_END	(MSP_USB1_BASE + 0x17)
41#define MSP_USB1_ID_START	(MSP_USB1_BASE + 0x40000)
42#define MSP_USB1_ID_END		(MSP_USB1_BASE + 0x4008f)
43#define MSP_USB1_HS_START	(MSP_USB1_BASE + 0x40100)
44#define MSP_USB1_HS_END		(MSP_USB1_BASE + 0x401ff)
45
46/* USB Identification registers */
47struct msp_usbid_regs {
48	u32 id;		/* 0x0: Identification register */
49	u32 hwgen;	/* 0x4: General HW params */
50	u32 hwhost;	/* 0x8: Host HW params */
51	u32 hwdev;	/* 0xc: Device HW params */
52	u32 hwtxbuf;	/* 0x10: Tx buffer HW params */
53	u32 hwrxbuf;	/* 0x14: Rx buffer HW params */
54	u32 reserved[26];
55	u32 timer0_load; /* 0x80: General-purpose timer 0 load*/
56	u32 timer0_ctrl; /* 0x84: General-purpose timer 0 control */
57	u32 timer1_load; /* 0x88: General-purpose timer 1 load*/
58	u32 timer1_ctrl; /* 0x8c: General-purpose timer 1 control */
59};
60
61/* MSBus to AMBA registers */
62struct msp_mab_regs {
63	u32 isr;	/* 0x0: Interrupt status */
64	u32 imr;	/* 0x4: Interrupt mask */
65	u32 thcr0;	/* 0x8: Transaction header capture 0 */
66	u32 thcr1;	/* 0xc: Transaction header capture 1 */
67	u32 int_stat;	/* 0x10: Interrupt status summary */
68	u32 phy_cfg;	/* 0x14: USB phy config */
69};
70
71/* EHCI registers */
72struct msp_usbhs_regs {
73	u32 hciver;	/* 0x0: Version and offset to operational regs */
74	u32 hcsparams;	/* 0x4: Host control structural parameters */
75	u32 hccparams;	/* 0x8: Host control capability parameters */
76	u32 reserved0[5];
77	u32 dciver;	/* 0x20: Device interface version */
78	u32 dccparams;	/* 0x24: Device control capability parameters */
79	u32 reserved1[6];
80	u32 cmd;	/* 0x40: USB command */
81	u32 sts;	/* 0x44: USB status */
82	u32 int_ena;	/* 0x48: USB interrupt enable */
83	u32 frindex;	/* 0x4c: Frame index */
84	u32 reserved3;
85	union {
86		struct {
87			u32 flb_addr; /* 0x54: Frame list base address */
88			u32 next_async_addr; /* 0x58: next asynchronous addr */
89			u32 ttctrl; /* 0x5c: embedded transaction translator
90							async buffer status */
91			u32 burst_size; /* 0x60: Controller burst size */
92			u32 tx_fifo_ctrl; /* 0x64: Tx latency FIFO tuning */
93			u32 reserved0[4];
94			u32 endpt_nak; /* 0x78: Endpoint NAK */
95			u32 endpt_nak_ena; /* 0x7c: Endpoint NAK enable */
96			u32 cfg_flag; /* 0x80: Config flag */
97			u32 port_sc1; /* 0x84: Port status & control 1 */
98			u32 reserved1[7];
99			u32 otgsc;	/* 0xa4: OTG status & control */
100			u32 mode;	/* 0xa8: USB controller mode */
101		} host;
102
103		struct {
104			u32 dev_addr; /* 0x54: Device address */
105			u32 endpt_list_addr; /* 0x58: Endpoint list address */
106			u32 reserved0[7];
107			u32 endpt_nak;	/* 0x74 */
108			u32 endpt_nak_ctrl; /* 0x78 */
109			u32 cfg_flag; /* 0x80 */
110			u32 port_sc1; /* 0x84: Port status & control 1 */
111			u32 reserved[7];
112			u32 otgsc;	/* 0xa4: OTG status & control */
113			u32 mode;	/* 0xa8: USB controller mode */
114			u32 endpt_setup_stat; /* 0xac */
115			u32 endpt_prime; /* 0xb0 */
116			u32 endpt_flush; /* 0xb4 */
117			u32 endpt_stat; /* 0xb8 */
118			u32 endpt_complete; /* 0xbc */
119			u32 endpt_ctrl0; /* 0xc0 */
120			u32 endpt_ctrl1; /* 0xc4 */
121			u32 endpt_ctrl2; /* 0xc8 */
122			u32 endpt_ctrl3; /* 0xcc */
123		} device;
124	} u;
125};
126/*
127 * Container for the more-generic platform_device.
128 * This exists mainly as a way to map the non-standard register
129 * spaces and make them accessible to the USB ISR.
130 */
131struct mspusb_device {
132	struct msp_mab_regs   __iomem *mab_regs;
133	struct msp_usbid_regs __iomem *usbid_regs;
134	struct msp_usbhs_regs __iomem *usbhs_regs;
135	struct platform_device dev;
136};
137
138#define to_mspusb_device(x) container_of((x), struct mspusb_device, dev)
139#define TO_HOST_ID(x) ((x) & 0x3)
140#endif /*MSP_USB_H_*/
141