1/ {
2	#address-cells = <1>;
3	#size-cells = <1>;
4	compatible = "brcm,bcm7360";
5
6	cpus {
7		#address-cells = <1>;
8		#size-cells = <0>;
9
10		mips-hpt-frequency = <375000000>;
11
12		cpu@0 {
13			compatible = "brcm,bmips3300";
14			device_type = "cpu";
15			reg = <0>;
16		};
17	};
18
19	aliases {
20		uart0 = &uart0;
21	};
22
23	cpu_intc: cpu_intc {
24		#address-cells = <0>;
25		compatible = "mti,cpu-interrupt-controller";
26
27		interrupt-controller;
28		#interrupt-cells = <1>;
29	};
30
31	clocks {
32		uart_clk: uart_clk {
33			compatible = "fixed-clock";
34			#clock-cells = <0>;
35			clock-frequency = <81000000>;
36		};
37	};
38
39	rdb {
40		#address-cells = <1>;
41		#size-cells = <1>;
42
43		compatible = "simple-bus";
44		ranges = <0 0x10000000 0x01000000>;
45
46		periph_intc: periph_intc@411400 {
47			compatible = "brcm,bcm7038-l1-intc";
48			reg = <0x411400 0x30>;
49
50			interrupt-controller;
51			#interrupt-cells = <1>;
52
53			interrupt-parent = <&cpu_intc>;
54			interrupts = <2>;
55		};
56
57		sun_l2_intc: sun_l2_intc@403000 {
58			compatible = "brcm,l2-intc";
59			reg = <0x403000 0x30>;
60			interrupt-controller;
61			#interrupt-cells = <1>;
62			interrupt-parent = <&periph_intc>;
63			interrupts = <48>;
64		};
65
66		gisb-arb@400000 {
67			compatible = "brcm,bcm7400-gisb-arb";
68			reg = <0x400000 0xdc>;
69			native-endian;
70			interrupt-parent = <&sun_l2_intc>;
71			interrupts = <0>, <2>;
72			brcm,gisb-arb-master-mask = <0x2f3>;
73			brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
74						     "rdc_0", "raaga_0",
75						     "avd_0", "jtag_0";
76		};
77
78		upg_irq0_intc: upg_irq0_intc@406600 {
79			compatible = "brcm,bcm7120-l2-intc";
80			reg = <0x406600 0x8>;
81
82			brcm,int-map-mask = <0x44>;
83			brcm,int-fwd-mask = <0x70000>;
84
85			interrupt-controller;
86			#interrupt-cells = <1>;
87
88			interrupt-parent = <&periph_intc>;
89			interrupts = <56>;
90		};
91
92		sun_top_ctrl: syscon@404000 {
93			compatible = "brcm,bcm7360-sun-top-ctrl", "syscon";
94			reg = <0x404000 0x51c>;
95			little-endian;
96		};
97
98		reboot {
99			compatible = "brcm,brcmstb-reboot";
100			syscon = <&sun_top_ctrl 0x304 0x308>;
101		};
102
103		uart0: serial@406800 {
104			compatible = "ns16550a";
105			reg = <0x406800 0x20>;
106			reg-io-width = <0x4>;
107			reg-shift = <0x2>;
108			native-endian;
109			interrupt-parent = <&periph_intc>;
110			interrupts = <61>;
111			clocks = <&uart_clk>;
112			status = "disabled";
113		};
114
115		enet0: ethernet@430000 {
116			phy-mode = "internal";
117			phy-handle = <&phy1>;
118			mac-address = [ 00 10 18 36 23 1a ];
119			compatible = "brcm,genet-v2";
120			#address-cells = <0x1>;
121			#size-cells = <0x1>;
122			reg = <0x430000 0x4c8c>;
123			interrupts = <24>, <25>;
124			interrupt-parent = <&periph_intc>;
125			status = "disabled";
126
127			mdio@e14 {
128				compatible = "brcm,genet-mdio-v2";
129				#address-cells = <0x1>;
130				#size-cells = <0x0>;
131				reg = <0xe14 0x8>;
132
133				phy1: ethernet-phy@1 {
134					max-speed = <100>;
135					reg = <0x1>;
136					compatible = "brcm,40nm-ephy",
137						"ethernet-phy-ieee802.3-c22";
138				};
139			};
140		};
141
142		ehci0: usb@480300 {
143			compatible = "brcm,bcm7360-ehci", "generic-ehci";
144			reg = <0x480300 0x100>;
145			native-endian;
146			interrupt-parent = <&periph_intc>;
147			interrupts = <65>;
148			status = "disabled";
149		};
150
151		ohci0: usb@480400 {
152			compatible = "brcm,bcm7360-ohci", "generic-ohci";
153			reg = <0x480400 0x100>;
154			native-endian;
155			no-big-frame-no;
156			interrupt-parent = <&periph_intc>;
157			interrupts = <66>;
158			status = "disabled";
159		};
160	};
161};
162