1/*
2 *  Atheros AR71XX/AR724X/AR913X specific setup
3 *
4 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
6 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
9 *
10 *  This program is free software; you can redistribute it and/or modify it
11 *  under the terms of the GNU General Public License version 2 as published
12 *  by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/bootmem.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20
21#include <asm/bootinfo.h>
22#include <asm/idle.h>
23#include <asm/time.h>		/* for mips_hpt_frequency */
24#include <asm/reboot.h>		/* for _machine_{restart,halt} */
25#include <asm/mips_machine.h>
26
27#include <asm/mach-ath79/ath79.h>
28#include <asm/mach-ath79/ar71xx_regs.h>
29#include "common.h"
30#include "dev-common.h"
31#include "machtypes.h"
32
33#define ATH79_SYS_TYPE_LEN	64
34
35#define AR71XX_BASE_FREQ	40000000
36#define AR724X_BASE_FREQ	5000000
37#define AR913X_BASE_FREQ	5000000
38
39static char ath79_sys_type[ATH79_SYS_TYPE_LEN];
40
41static void ath79_restart(char *command)
42{
43	ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
44	for (;;)
45		if (cpu_wait)
46			cpu_wait();
47}
48
49static void ath79_halt(void)
50{
51	while (1)
52		cpu_wait();
53}
54
55static void __init ath79_detect_sys_type(void)
56{
57	char *chip = "????";
58	u32 id;
59	u32 major;
60	u32 minor;
61	u32 rev = 0;
62
63	id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
64	major = id & REV_ID_MAJOR_MASK;
65
66	switch (major) {
67	case REV_ID_MAJOR_AR71XX:
68		minor = id & AR71XX_REV_ID_MINOR_MASK;
69		rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
70		rev &= AR71XX_REV_ID_REVISION_MASK;
71		switch (minor) {
72		case AR71XX_REV_ID_MINOR_AR7130:
73			ath79_soc = ATH79_SOC_AR7130;
74			chip = "7130";
75			break;
76
77		case AR71XX_REV_ID_MINOR_AR7141:
78			ath79_soc = ATH79_SOC_AR7141;
79			chip = "7141";
80			break;
81
82		case AR71XX_REV_ID_MINOR_AR7161:
83			ath79_soc = ATH79_SOC_AR7161;
84			chip = "7161";
85			break;
86		}
87		break;
88
89	case REV_ID_MAJOR_AR7240:
90		ath79_soc = ATH79_SOC_AR7240;
91		chip = "7240";
92		rev = id & AR724X_REV_ID_REVISION_MASK;
93		break;
94
95	case REV_ID_MAJOR_AR7241:
96		ath79_soc = ATH79_SOC_AR7241;
97		chip = "7241";
98		rev = id & AR724X_REV_ID_REVISION_MASK;
99		break;
100
101	case REV_ID_MAJOR_AR7242:
102		ath79_soc = ATH79_SOC_AR7242;
103		chip = "7242";
104		rev = id & AR724X_REV_ID_REVISION_MASK;
105		break;
106
107	case REV_ID_MAJOR_AR913X:
108		minor = id & AR913X_REV_ID_MINOR_MASK;
109		rev = id >> AR913X_REV_ID_REVISION_SHIFT;
110		rev &= AR913X_REV_ID_REVISION_MASK;
111		switch (minor) {
112		case AR913X_REV_ID_MINOR_AR9130:
113			ath79_soc = ATH79_SOC_AR9130;
114			chip = "9130";
115			break;
116
117		case AR913X_REV_ID_MINOR_AR9132:
118			ath79_soc = ATH79_SOC_AR9132;
119			chip = "9132";
120			break;
121		}
122		break;
123
124	case REV_ID_MAJOR_AR9330:
125		ath79_soc = ATH79_SOC_AR9330;
126		chip = "9330";
127		rev = id & AR933X_REV_ID_REVISION_MASK;
128		break;
129
130	case REV_ID_MAJOR_AR9331:
131		ath79_soc = ATH79_SOC_AR9331;
132		chip = "9331";
133		rev = id & AR933X_REV_ID_REVISION_MASK;
134		break;
135
136	case REV_ID_MAJOR_AR9341:
137		ath79_soc = ATH79_SOC_AR9341;
138		chip = "9341";
139		rev = id & AR934X_REV_ID_REVISION_MASK;
140		break;
141
142	case REV_ID_MAJOR_AR9342:
143		ath79_soc = ATH79_SOC_AR9342;
144		chip = "9342";
145		rev = id & AR934X_REV_ID_REVISION_MASK;
146		break;
147
148	case REV_ID_MAJOR_AR9344:
149		ath79_soc = ATH79_SOC_AR9344;
150		chip = "9344";
151		rev = id & AR934X_REV_ID_REVISION_MASK;
152		break;
153
154	case REV_ID_MAJOR_QCA9556:
155		ath79_soc = ATH79_SOC_QCA9556;
156		chip = "9556";
157		rev = id & QCA955X_REV_ID_REVISION_MASK;
158		break;
159
160	case REV_ID_MAJOR_QCA9558:
161		ath79_soc = ATH79_SOC_QCA9558;
162		chip = "9558";
163		rev = id & QCA955X_REV_ID_REVISION_MASK;
164		break;
165
166	default:
167		panic("ath79: unknown SoC, id:0x%08x", id);
168	}
169
170	ath79_soc_rev = rev;
171
172	if (soc_is_qca955x())
173		sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
174			chip, rev);
175	else
176		sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
177	pr_info("SoC: %s\n", ath79_sys_type);
178}
179
180const char *get_system_type(void)
181{
182	return ath79_sys_type;
183}
184
185int get_c0_perfcount_int(void)
186{
187	return ATH79_MISC_IRQ(5);
188}
189EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
190
191unsigned int get_c0_compare_int(void)
192{
193	return CP0_LEGACY_COMPARE_IRQ;
194}
195
196void __init plat_mem_setup(void)
197{
198	set_io_port_base(KSEG1);
199
200	ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
201					   AR71XX_RESET_SIZE);
202	ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
203					 AR71XX_PLL_SIZE);
204	ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
205					 AR71XX_DDR_CTRL_SIZE);
206
207	ath79_detect_sys_type();
208	detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
209
210	_machine_restart = ath79_restart;
211	_machine_halt = ath79_halt;
212	pm_power_off = ath79_halt;
213}
214
215void __init plat_time_init(void)
216{
217	unsigned long cpu_clk_rate;
218	unsigned long ahb_clk_rate;
219	unsigned long ddr_clk_rate;
220	unsigned long ref_clk_rate;
221
222	ath79_clocks_init();
223
224	cpu_clk_rate = ath79_get_sys_clk_rate("cpu");
225	ahb_clk_rate = ath79_get_sys_clk_rate("ahb");
226	ddr_clk_rate = ath79_get_sys_clk_rate("ddr");
227	ref_clk_rate = ath79_get_sys_clk_rate("ref");
228
229	pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz\n",
230		cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000,
231		ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000,
232		ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000,
233		ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000);
234
235	mips_hpt_frequency = cpu_clk_rate / 2;
236}
237
238static int __init ath79_setup(void)
239{
240	ath79_gpio_init();
241	ath79_register_uart();
242	ath79_register_wdt();
243
244	mips_machine_setup();
245
246	return 0;
247}
248
249arch_initcall(ath79_setup);
250
251static void __init ath79_generic_init(void)
252{
253	/* Nothing to do */
254}
255
256MIPS_MACHINE(ATH79_MACH_GENERIC,
257	     "Generic",
258	     "Generic AR71XX/AR724X/AR913X based board",
259	     ath79_generic_init);
260