1/*
2 * Architecture-specific setup.
3 *
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 *	David Mosberger-Tang <davidm@hpl.hp.com>
6 *	Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, 2004 Intel Corp
8 * 	Rohit Seth <rohit.seth@intel.com>
9 * 	Suresh Siddha <suresh.b.siddha@intel.com>
10 * 	Gordon Jin <gordon.jin@intel.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 *
14 * 12/26/04 S.Siddha, G.Jin, R.Seth
15 *			Add multi-threading and multi-core detection
16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
18 * 03/31/00 R.Seth	cpu_initialized and current->processor fixes
19 * 02/04/00 D.Mosberger	some more get_cpuinfo fixes...
20 * 02/01/00 R.Seth	fixed get_cpuinfo for SMP
21 * 01/07/99 S.Eranian	added the support for command line argument
22 * 06/24/99 W.Drummond	added boot_cpu_data.
23 * 05/28/05 Z. Menyhart	Dynamic stride size for "flush_icache_range()"
24 */
25#include <linux/module.h>
26#include <linux/init.h>
27
28#include <linux/acpi.h>
29#include <linux/bootmem.h>
30#include <linux/console.h>
31#include <linux/delay.h>
32#include <linux/kernel.h>
33#include <linux/reboot.h>
34#include <linux/sched.h>
35#include <linux/seq_file.h>
36#include <linux/string.h>
37#include <linux/threads.h>
38#include <linux/screen_info.h>
39#include <linux/dmi.h>
40#include <linux/serial.h>
41#include <linux/serial_core.h>
42#include <linux/efi.h>
43#include <linux/initrd.h>
44#include <linux/pm.h>
45#include <linux/cpufreq.h>
46#include <linux/kexec.h>
47#include <linux/crash_dump.h>
48
49#include <asm/machvec.h>
50#include <asm/mca.h>
51#include <asm/meminit.h>
52#include <asm/page.h>
53#include <asm/paravirt.h>
54#include <asm/paravirt_patch.h>
55#include <asm/patch.h>
56#include <asm/pgtable.h>
57#include <asm/processor.h>
58#include <asm/sal.h>
59#include <asm/sections.h>
60#include <asm/setup.h>
61#include <asm/smp.h>
62#include <asm/tlbflush.h>
63#include <asm/unistd.h>
64#include <asm/hpsim.h>
65
66#if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
67# error "struct cpuinfo_ia64 too big!"
68#endif
69
70#ifdef CONFIG_SMP
71unsigned long __per_cpu_offset[NR_CPUS];
72EXPORT_SYMBOL(__per_cpu_offset);
73#endif
74
75DEFINE_PER_CPU(struct cpuinfo_ia64, ia64_cpu_info);
76DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
77unsigned long ia64_cycles_per_usec;
78struct ia64_boot_param *ia64_boot_param;
79struct screen_info screen_info;
80unsigned long vga_console_iobase;
81unsigned long vga_console_membase;
82
83static struct resource data_resource = {
84	.name	= "Kernel data",
85	.flags	= IORESOURCE_BUSY | IORESOURCE_MEM
86};
87
88static struct resource code_resource = {
89	.name	= "Kernel code",
90	.flags	= IORESOURCE_BUSY | IORESOURCE_MEM
91};
92
93static struct resource bss_resource = {
94	.name	= "Kernel bss",
95	.flags	= IORESOURCE_BUSY | IORESOURCE_MEM
96};
97
98unsigned long ia64_max_cacheline_size;
99
100unsigned long ia64_iobase;	/* virtual address for I/O accesses */
101EXPORT_SYMBOL(ia64_iobase);
102struct io_space io_space[MAX_IO_SPACES];
103EXPORT_SYMBOL(io_space);
104unsigned int num_io_spaces;
105
106/*
107 * "flush_icache_range()" needs to know what processor dependent stride size to use
108 * when it makes i-cache(s) coherent with d-caches.
109 */
110#define	I_CACHE_STRIDE_SHIFT	5	/* Safest way to go: 32 bytes by 32 bytes */
111unsigned long ia64_i_cache_stride_shift = ~0;
112/*
113 * "clflush_cache_range()" needs to know what processor dependent stride size to
114 * use when it flushes cache lines including both d-cache and i-cache.
115 */
116/* Safest way to go: 32 bytes by 32 bytes */
117#define	CACHE_STRIDE_SHIFT	5
118unsigned long ia64_cache_stride_shift = ~0;
119
120/*
121 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1).  This
122 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
123 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
124 * address of the second buffer must be aligned to (merge_mask+1) in order to be
125 * mergeable).  By default, we assume there is no I/O MMU which can merge physically
126 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
127 * page-size of 2^64.
128 */
129unsigned long ia64_max_iommu_merge_mask = ~0UL;
130EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
131
132/*
133 * We use a special marker for the end of memory and it uses the extra (+1) slot
134 */
135struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata;
136int num_rsvd_regions __initdata;
137
138
139/*
140 * Filter incoming memory segments based on the primitive map created from the boot
141 * parameters. Segments contained in the map are removed from the memory ranges. A
142 * caller-specified function is called with the memory ranges that remain after filtering.
143 * This routine does not assume the incoming segments are sorted.
144 */
145int __init
146filter_rsvd_memory (u64 start, u64 end, void *arg)
147{
148	u64 range_start, range_end, prev_start;
149	void (*func)(unsigned long, unsigned long, int);
150	int i;
151
152#if IGNORE_PFN0
153	if (start == PAGE_OFFSET) {
154		printk(KERN_WARNING "warning: skipping physical page 0\n");
155		start += PAGE_SIZE;
156		if (start >= end) return 0;
157	}
158#endif
159	/*
160	 * lowest possible address(walker uses virtual)
161	 */
162	prev_start = PAGE_OFFSET;
163	func = arg;
164
165	for (i = 0; i < num_rsvd_regions; ++i) {
166		range_start = max(start, prev_start);
167		range_end   = min(end, rsvd_region[i].start);
168
169		if (range_start < range_end)
170			call_pernode_memory(__pa(range_start), range_end - range_start, func);
171
172		/* nothing more available in this segment */
173		if (range_end == end) return 0;
174
175		prev_start = rsvd_region[i].end;
176	}
177	/* end of memory marker allows full processing inside loop body */
178	return 0;
179}
180
181/*
182 * Similar to "filter_rsvd_memory()", but the reserved memory ranges
183 * are not filtered out.
184 */
185int __init
186filter_memory(u64 start, u64 end, void *arg)
187{
188	void (*func)(unsigned long, unsigned long, int);
189
190#if IGNORE_PFN0
191	if (start == PAGE_OFFSET) {
192		printk(KERN_WARNING "warning: skipping physical page 0\n");
193		start += PAGE_SIZE;
194		if (start >= end)
195			return 0;
196	}
197#endif
198	func = arg;
199	if (start < end)
200		call_pernode_memory(__pa(start), end - start, func);
201	return 0;
202}
203
204static void __init
205sort_regions (struct rsvd_region *rsvd_region, int max)
206{
207	int j;
208
209	/* simple bubble sorting */
210	while (max--) {
211		for (j = 0; j < max; ++j) {
212			if (rsvd_region[j].start > rsvd_region[j+1].start) {
213				struct rsvd_region tmp;
214				tmp = rsvd_region[j];
215				rsvd_region[j] = rsvd_region[j + 1];
216				rsvd_region[j + 1] = tmp;
217			}
218		}
219	}
220}
221
222/* merge overlaps */
223static int __init
224merge_regions (struct rsvd_region *rsvd_region, int max)
225{
226	int i;
227	for (i = 1; i < max; ++i) {
228		if (rsvd_region[i].start >= rsvd_region[i-1].end)
229			continue;
230		if (rsvd_region[i].end > rsvd_region[i-1].end)
231			rsvd_region[i-1].end = rsvd_region[i].end;
232		--max;
233		memmove(&rsvd_region[i], &rsvd_region[i+1],
234			(max - i) * sizeof(struct rsvd_region));
235	}
236	return max;
237}
238
239/*
240 * Request address space for all standard resources
241 */
242static int __init register_memory(void)
243{
244	code_resource.start = ia64_tpa(_text);
245	code_resource.end   = ia64_tpa(_etext) - 1;
246	data_resource.start = ia64_tpa(_etext);
247	data_resource.end   = ia64_tpa(_edata) - 1;
248	bss_resource.start  = ia64_tpa(__bss_start);
249	bss_resource.end    = ia64_tpa(_end) - 1;
250	efi_initialize_iomem_resources(&code_resource, &data_resource,
251			&bss_resource);
252
253	return 0;
254}
255
256__initcall(register_memory);
257
258
259#ifdef CONFIG_KEXEC
260
261/*
262 * This function checks if the reserved crashkernel is allowed on the specific
263 * IA64 machine flavour. Machines without an IO TLB use swiotlb and require
264 * some memory below 4 GB (i.e. in 32 bit area), see the implementation of
265 * lib/swiotlb.c. The hpzx1 architecture has an IO TLB but cannot use that
266 * in kdump case. See the comment in sba_init() in sba_iommu.c.
267 *
268 * So, the only machvec that really supports loading the kdump kernel
269 * over 4 GB is "sn2".
270 */
271static int __init check_crashkernel_memory(unsigned long pbase, size_t size)
272{
273	if (ia64_platform_is("sn2") || ia64_platform_is("uv"))
274		return 1;
275	else
276		return pbase < (1UL << 32);
277}
278
279static void __init setup_crashkernel(unsigned long total, int *n)
280{
281	unsigned long long base = 0, size = 0;
282	int ret;
283
284	ret = parse_crashkernel(boot_command_line, total,
285			&size, &base);
286	if (ret == 0 && size > 0) {
287		if (!base) {
288			sort_regions(rsvd_region, *n);
289			*n = merge_regions(rsvd_region, *n);
290			base = kdump_find_rsvd_region(size,
291					rsvd_region, *n);
292		}
293
294		if (!check_crashkernel_memory(base, size)) {
295			pr_warning("crashkernel: There would be kdump memory "
296				"at %ld GB but this is unusable because it "
297				"must\nbe below 4 GB. Change the memory "
298				"configuration of the machine.\n",
299				(unsigned long)(base >> 30));
300			return;
301		}
302
303		if (base != ~0UL) {
304			printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
305					"for crashkernel (System RAM: %ldMB)\n",
306					(unsigned long)(size >> 20),
307					(unsigned long)(base >> 20),
308					(unsigned long)(total >> 20));
309			rsvd_region[*n].start =
310				(unsigned long)__va(base);
311			rsvd_region[*n].end =
312				(unsigned long)__va(base + size);
313			(*n)++;
314			crashk_res.start = base;
315			crashk_res.end = base + size - 1;
316		}
317	}
318	efi_memmap_res.start = ia64_boot_param->efi_memmap;
319	efi_memmap_res.end = efi_memmap_res.start +
320		ia64_boot_param->efi_memmap_size;
321	boot_param_res.start = __pa(ia64_boot_param);
322	boot_param_res.end = boot_param_res.start +
323		sizeof(*ia64_boot_param);
324}
325#else
326static inline void __init setup_crashkernel(unsigned long total, int *n)
327{}
328#endif
329
330/**
331 * reserve_memory - setup reserved memory areas
332 *
333 * Setup the reserved memory areas set aside for the boot parameters,
334 * initrd, etc.  There are currently %IA64_MAX_RSVD_REGIONS defined,
335 * see arch/ia64/include/asm/meminit.h if you need to define more.
336 */
337void __init
338reserve_memory (void)
339{
340	int n = 0;
341	unsigned long total_memory;
342
343	/*
344	 * none of the entries in this table overlap
345	 */
346	rsvd_region[n].start = (unsigned long) ia64_boot_param;
347	rsvd_region[n].end   = rsvd_region[n].start + sizeof(*ia64_boot_param);
348	n++;
349
350	rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
351	rsvd_region[n].end   = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
352	n++;
353
354	rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
355	rsvd_region[n].end   = (rsvd_region[n].start
356				+ strlen(__va(ia64_boot_param->command_line)) + 1);
357	n++;
358
359	rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
360	rsvd_region[n].end   = (unsigned long) ia64_imva(_end);
361	n++;
362
363	n += paravirt_reserve_memory(&rsvd_region[n]);
364
365#ifdef CONFIG_BLK_DEV_INITRD
366	if (ia64_boot_param->initrd_start) {
367		rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
368		rsvd_region[n].end   = rsvd_region[n].start + ia64_boot_param->initrd_size;
369		n++;
370	}
371#endif
372
373#ifdef CONFIG_CRASH_DUMP
374	if (reserve_elfcorehdr(&rsvd_region[n].start,
375			       &rsvd_region[n].end) == 0)
376		n++;
377#endif
378
379	total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end);
380	n++;
381
382	setup_crashkernel(total_memory, &n);
383
384	/* end of memory marker */
385	rsvd_region[n].start = ~0UL;
386	rsvd_region[n].end   = ~0UL;
387	n++;
388
389	num_rsvd_regions = n;
390	BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n);
391
392	sort_regions(rsvd_region, num_rsvd_regions);
393	num_rsvd_regions = merge_regions(rsvd_region, num_rsvd_regions);
394}
395
396
397/**
398 * find_initrd - get initrd parameters from the boot parameter structure
399 *
400 * Grab the initrd start and end from the boot parameter struct given us by
401 * the boot loader.
402 */
403void __init
404find_initrd (void)
405{
406#ifdef CONFIG_BLK_DEV_INITRD
407	if (ia64_boot_param->initrd_start) {
408		initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
409		initrd_end   = initrd_start+ia64_boot_param->initrd_size;
410
411		printk(KERN_INFO "Initial ramdisk at: 0x%lx (%llu bytes)\n",
412		       initrd_start, ia64_boot_param->initrd_size);
413	}
414#endif
415}
416
417static void __init
418io_port_init (void)
419{
420	unsigned long phys_iobase;
421
422	/*
423	 * Set `iobase' based on the EFI memory map or, failing that, the
424	 * value firmware left in ar.k0.
425	 *
426	 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute
427	 * the port's virtual address, so ia32_load_state() loads it with a
428	 * user virtual address.  But in ia64 mode, glibc uses the
429	 * *physical* address in ar.k0 to mmap the appropriate area from
430	 * /dev/mem, and the inX()/outX() interfaces use MMIO.  In both
431	 * cases, user-mode can only use the legacy 0-64K I/O port space.
432	 *
433	 * ar.k0 is not involved in kernel I/O port accesses, which can use
434	 * any of the I/O port spaces and are done via MMIO using the
435	 * virtual mmio_base from the appropriate io_space[].
436	 */
437	phys_iobase = efi_get_iobase();
438	if (!phys_iobase) {
439		phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
440		printk(KERN_INFO "No I/O port range found in EFI memory map, "
441			"falling back to AR.KR0 (0x%lx)\n", phys_iobase);
442	}
443	ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
444	ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
445
446	/* setup legacy IO port space */
447	io_space[0].mmio_base = ia64_iobase;
448	io_space[0].sparse = 1;
449	num_io_spaces = 1;
450}
451
452/**
453 * early_console_setup - setup debugging console
454 *
455 * Consoles started here require little enough setup that we can start using
456 * them very early in the boot process, either right after the machine
457 * vector initialization, or even before if the drivers can detect their hw.
458 *
459 * Returns non-zero if a console couldn't be setup.
460 */
461static inline int __init
462early_console_setup (char *cmdline)
463{
464	int earlycons = 0;
465
466#ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
467	{
468		extern int sn_serial_console_early_setup(void);
469		if (!sn_serial_console_early_setup())
470			earlycons++;
471	}
472#endif
473#ifdef CONFIG_EFI_PCDP
474	if (!efi_setup_pcdp_console(cmdline))
475		earlycons++;
476#endif
477	if (!simcons_register())
478		earlycons++;
479
480	return (earlycons) ? 0 : -1;
481}
482
483static inline void
484mark_bsp_online (void)
485{
486#ifdef CONFIG_SMP
487	/* If we register an early console, allow CPU 0 to printk */
488	set_cpu_online(smp_processor_id(), true);
489#endif
490}
491
492static __initdata int nomca;
493static __init int setup_nomca(char *s)
494{
495	nomca = 1;
496	return 0;
497}
498early_param("nomca", setup_nomca);
499
500#ifdef CONFIG_CRASH_DUMP
501int __init reserve_elfcorehdr(u64 *start, u64 *end)
502{
503	u64 length;
504
505	/* We get the address using the kernel command line,
506	 * but the size is extracted from the EFI tables.
507	 * Both address and size are required for reservation
508	 * to work properly.
509	 */
510
511	if (!is_vmcore_usable())
512		return -EINVAL;
513
514	if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) {
515		vmcore_unusable();
516		return -EINVAL;
517	}
518
519	*start = (unsigned long)__va(elfcorehdr_addr);
520	*end = *start + length;
521	return 0;
522}
523
524#endif /* CONFIG_PROC_VMCORE */
525
526void __init
527setup_arch (char **cmdline_p)
528{
529	unw_init();
530
531	paravirt_arch_setup_early();
532
533	ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
534	paravirt_patch_apply();
535
536	*cmdline_p = __va(ia64_boot_param->command_line);
537	strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
538
539	efi_init();
540	io_port_init();
541
542#ifdef CONFIG_IA64_GENERIC
543	/* machvec needs to be parsed from the command line
544	 * before parse_early_param() is called to ensure
545	 * that ia64_mv is initialised before any command line
546	 * settings may cause console setup to occur
547	 */
548	machvec_init_from_cmdline(*cmdline_p);
549#endif
550
551	parse_early_param();
552
553	if (early_console_setup(*cmdline_p) == 0)
554		mark_bsp_online();
555
556#ifdef CONFIG_ACPI
557	/* Initialize the ACPI boot-time table parser */
558	acpi_table_init();
559	early_acpi_boot_init();
560# ifdef CONFIG_ACPI_NUMA
561	acpi_numa_init();
562#  ifdef CONFIG_ACPI_HOTPLUG_CPU
563	prefill_possible_map();
564#  endif
565	per_cpu_scan_finalize((cpumask_weight(&early_cpu_possible_map) == 0 ?
566		32 : cpumask_weight(&early_cpu_possible_map)),
567		additional_cpus > 0 ? additional_cpus : 0);
568# endif
569#endif /* CONFIG_APCI_BOOT */
570
571#ifdef CONFIG_SMP
572	smp_build_cpu_map();
573#endif
574	find_memory();
575
576	/* process SAL system table: */
577	ia64_sal_init(__va(efi.sal_systab));
578
579#ifdef CONFIG_ITANIUM
580	ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist);
581#else
582	{
583		unsigned long num_phys_stacked;
584
585		if (ia64_pal_rse_info(&num_phys_stacked, 0) == 0 && num_phys_stacked > 96)
586			ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist);
587	}
588#endif
589
590#ifdef CONFIG_SMP
591	cpu_physical_id(0) = hard_smp_processor_id();
592#endif
593
594	cpu_init();	/* initialize the bootstrap CPU */
595	mmu_context_init();	/* initialize context_id bitmap */
596
597	paravirt_banner();
598	paravirt_arch_setup_console(cmdline_p);
599
600#ifdef CONFIG_VT
601	if (!conswitchp) {
602# if defined(CONFIG_DUMMY_CONSOLE)
603		conswitchp = &dummy_con;
604# endif
605# if defined(CONFIG_VGA_CONSOLE)
606		/*
607		 * Non-legacy systems may route legacy VGA MMIO range to system
608		 * memory.  vga_con probes the MMIO hole, so memory looks like
609		 * a VGA device to it.  The EFI memory map can tell us if it's
610		 * memory so we can avoid this problem.
611		 */
612		if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
613			conswitchp = &vga_con;
614# endif
615	}
616#endif
617
618	/* enable IA-64 Machine Check Abort Handling unless disabled */
619	if (paravirt_arch_setup_nomca())
620		nomca = 1;
621	if (!nomca)
622		ia64_mca_init();
623
624	platform_setup(cmdline_p);
625#ifndef CONFIG_IA64_HP_SIM
626	check_sal_cache_flush();
627#endif
628	paging_init();
629}
630
631/*
632 * Display cpu info for all CPUs.
633 */
634static int
635show_cpuinfo (struct seq_file *m, void *v)
636{
637#ifdef CONFIG_SMP
638#	define lpj	c->loops_per_jiffy
639#	define cpunum	c->cpu
640#else
641#	define lpj	loops_per_jiffy
642#	define cpunum	0
643#endif
644	static struct {
645		unsigned long mask;
646		const char *feature_name;
647	} feature_bits[] = {
648		{ 1UL << 0, "branchlong" },
649		{ 1UL << 1, "spontaneous deferral"},
650		{ 1UL << 2, "16-byte atomic ops" }
651	};
652	char features[128], *cp, *sep;
653	struct cpuinfo_ia64 *c = v;
654	unsigned long mask;
655	unsigned long proc_freq;
656	int i, size;
657
658	mask = c->features;
659
660	/* build the feature string: */
661	memcpy(features, "standard", 9);
662	cp = features;
663	size = sizeof(features);
664	sep = "";
665	for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) {
666		if (mask & feature_bits[i].mask) {
667			cp += snprintf(cp, size, "%s%s", sep,
668				       feature_bits[i].feature_name),
669			sep = ", ";
670			mask &= ~feature_bits[i].mask;
671			size = sizeof(features) - (cp - features);
672		}
673	}
674	if (mask && size > 1) {
675		/* print unknown features as a hex value */
676		snprintf(cp, size, "%s0x%lx", sep, mask);
677	}
678
679	proc_freq = cpufreq_quick_get(cpunum);
680	if (!proc_freq)
681		proc_freq = c->proc_freq / 1000;
682
683	seq_printf(m,
684		   "processor  : %d\n"
685		   "vendor     : %s\n"
686		   "arch       : IA-64\n"
687		   "family     : %u\n"
688		   "model      : %u\n"
689		   "model name : %s\n"
690		   "revision   : %u\n"
691		   "archrev    : %u\n"
692		   "features   : %s\n"
693		   "cpu number : %lu\n"
694		   "cpu regs   : %u\n"
695		   "cpu MHz    : %lu.%03lu\n"
696		   "itc MHz    : %lu.%06lu\n"
697		   "BogoMIPS   : %lu.%02lu\n",
698		   cpunum, c->vendor, c->family, c->model,
699		   c->model_name, c->revision, c->archrev,
700		   features, c->ppn, c->number,
701		   proc_freq / 1000, proc_freq % 1000,
702		   c->itc_freq / 1000000, c->itc_freq % 1000000,
703		   lpj*HZ/500000, (lpj*HZ/5000) % 100);
704#ifdef CONFIG_SMP
705	seq_printf(m, "siblings   : %u\n",
706		   cpumask_weight(&cpu_core_map[cpunum]));
707	if (c->socket_id != -1)
708		seq_printf(m, "physical id: %u\n", c->socket_id);
709	if (c->threads_per_core > 1 || c->cores_per_socket > 1)
710		seq_printf(m,
711			   "core id    : %u\n"
712			   "thread id  : %u\n",
713			   c->core_id, c->thread_id);
714#endif
715	seq_printf(m,"\n");
716
717	return 0;
718}
719
720static void *
721c_start (struct seq_file *m, loff_t *pos)
722{
723#ifdef CONFIG_SMP
724	while (*pos < nr_cpu_ids && !cpu_online(*pos))
725		++*pos;
726#endif
727	return *pos < nr_cpu_ids ? cpu_data(*pos) : NULL;
728}
729
730static void *
731c_next (struct seq_file *m, void *v, loff_t *pos)
732{
733	++*pos;
734	return c_start(m, pos);
735}
736
737static void
738c_stop (struct seq_file *m, void *v)
739{
740}
741
742const struct seq_operations cpuinfo_op = {
743	.start =	c_start,
744	.next =		c_next,
745	.stop =		c_stop,
746	.show =		show_cpuinfo
747};
748
749#define MAX_BRANDS	8
750static char brandname[MAX_BRANDS][128];
751
752static char *
753get_model_name(__u8 family, __u8 model)
754{
755	static int overflow;
756	char brand[128];
757	int i;
758
759	memcpy(brand, "Unknown", 8);
760	if (ia64_pal_get_brand_info(brand)) {
761		if (family == 0x7)
762			memcpy(brand, "Merced", 7);
763		else if (family == 0x1f) switch (model) {
764			case 0: memcpy(brand, "McKinley", 9); break;
765			case 1: memcpy(brand, "Madison", 8); break;
766			case 2: memcpy(brand, "Madison up to 9M cache", 23); break;
767		}
768	}
769	for (i = 0; i < MAX_BRANDS; i++)
770		if (strcmp(brandname[i], brand) == 0)
771			return brandname[i];
772	for (i = 0; i < MAX_BRANDS; i++)
773		if (brandname[i][0] == '\0')
774			return strcpy(brandname[i], brand);
775	if (overflow++ == 0)
776		printk(KERN_ERR
777		       "%s: Table overflow. Some processor model information will be missing\n",
778		       __func__);
779	return "Unknown";
780}
781
782static void
783identify_cpu (struct cpuinfo_ia64 *c)
784{
785	union {
786		unsigned long bits[5];
787		struct {
788			/* id 0 & 1: */
789			char vendor[16];
790
791			/* id 2 */
792			u64 ppn;		/* processor serial number */
793
794			/* id 3: */
795			unsigned number		:  8;
796			unsigned revision	:  8;
797			unsigned model		:  8;
798			unsigned family		:  8;
799			unsigned archrev	:  8;
800			unsigned reserved	: 24;
801
802			/* id 4: */
803			u64 features;
804		} field;
805	} cpuid;
806	pal_vm_info_1_u_t vm1;
807	pal_vm_info_2_u_t vm2;
808	pal_status_t status;
809	unsigned long impl_va_msb = 50, phys_addr_size = 44;	/* Itanium defaults */
810	int i;
811	for (i = 0; i < 5; ++i)
812		cpuid.bits[i] = ia64_get_cpuid(i);
813
814	memcpy(c->vendor, cpuid.field.vendor, 16);
815#ifdef CONFIG_SMP
816	c->cpu = smp_processor_id();
817
818	/* below default values will be overwritten  by identify_siblings()
819	 * for Multi-Threading/Multi-Core capable CPUs
820	 */
821	c->threads_per_core = c->cores_per_socket = c->num_log = 1;
822	c->socket_id = -1;
823
824	identify_siblings(c);
825
826	if (c->threads_per_core > smp_num_siblings)
827		smp_num_siblings = c->threads_per_core;
828#endif
829	c->ppn = cpuid.field.ppn;
830	c->number = cpuid.field.number;
831	c->revision = cpuid.field.revision;
832	c->model = cpuid.field.model;
833	c->family = cpuid.field.family;
834	c->archrev = cpuid.field.archrev;
835	c->features = cpuid.field.features;
836	c->model_name = get_model_name(c->family, c->model);
837
838	status = ia64_pal_vm_summary(&vm1, &vm2);
839	if (status == PAL_STATUS_SUCCESS) {
840		impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
841		phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
842	}
843	c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
844	c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
845}
846
847/*
848 * Do the following calculations:
849 *
850 * 1. the max. cache line size.
851 * 2. the minimum of the i-cache stride sizes for "flush_icache_range()".
852 * 3. the minimum of the cache stride sizes for "clflush_cache_range()".
853 */
854static void
855get_cache_info(void)
856{
857	unsigned long line_size, max = 1;
858	unsigned long l, levels, unique_caches;
859	pal_cache_config_info_t cci;
860	long status;
861
862        status = ia64_pal_cache_summary(&levels, &unique_caches);
863        if (status != 0) {
864                printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
865                       __func__, status);
866                max = SMP_CACHE_BYTES;
867		/* Safest setup for "flush_icache_range()" */
868		ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
869		/* Safest setup for "clflush_cache_range()" */
870		ia64_cache_stride_shift = CACHE_STRIDE_SHIFT;
871		goto out;
872        }
873
874	for (l = 0; l < levels; ++l) {
875		/* cache_type (data_or_unified)=2 */
876		status = ia64_pal_cache_config_info(l, 2, &cci);
877		if (status != 0) {
878			printk(KERN_ERR "%s: ia64_pal_cache_config_info"
879				"(l=%lu, 2) failed (status=%ld)\n",
880				__func__, l, status);
881			max = SMP_CACHE_BYTES;
882			/* The safest setup for "flush_icache_range()" */
883			cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
884			/* The safest setup for "clflush_cache_range()" */
885			ia64_cache_stride_shift = CACHE_STRIDE_SHIFT;
886			cci.pcci_unified = 1;
887		} else {
888			if (cci.pcci_stride < ia64_cache_stride_shift)
889				ia64_cache_stride_shift = cci.pcci_stride;
890
891			line_size = 1 << cci.pcci_line_size;
892			if (line_size > max)
893				max = line_size;
894		}
895
896		if (!cci.pcci_unified) {
897			/* cache_type (instruction)=1*/
898			status = ia64_pal_cache_config_info(l, 1, &cci);
899			if (status != 0) {
900				printk(KERN_ERR "%s: ia64_pal_cache_config_info"
901					"(l=%lu, 1) failed (status=%ld)\n",
902					__func__, l, status);
903				/* The safest setup for flush_icache_range() */
904				cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
905			}
906		}
907		if (cci.pcci_stride < ia64_i_cache_stride_shift)
908			ia64_i_cache_stride_shift = cci.pcci_stride;
909	}
910  out:
911	if (max > ia64_max_cacheline_size)
912		ia64_max_cacheline_size = max;
913}
914
915/*
916 * cpu_init() initializes state that is per-CPU.  This function acts
917 * as a 'CPU state barrier', nothing should get across.
918 */
919void
920cpu_init (void)
921{
922	extern void ia64_mmu_init(void *);
923	static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG;
924	unsigned long num_phys_stacked;
925	pal_vm_info_2_u_t vmi;
926	unsigned int max_ctx;
927	struct cpuinfo_ia64 *cpu_info;
928	void *cpu_data;
929
930	cpu_data = per_cpu_init();
931#ifdef CONFIG_SMP
932	/*
933	 * insert boot cpu into sibling and core mapes
934	 * (must be done after per_cpu area is setup)
935	 */
936	if (smp_processor_id() == 0) {
937		cpumask_set_cpu(0, &per_cpu(cpu_sibling_map, 0));
938		cpumask_set_cpu(0, &cpu_core_map[0]);
939	} else {
940		/*
941		 * Set ar.k3 so that assembly code in MCA handler can compute
942		 * physical addresses of per cpu variables with a simple:
943		 *   phys = ar.k3 + &per_cpu_var
944		 * and the alt-dtlb-miss handler can set per-cpu mapping into
945		 * the TLB when needed. head.S already did this for cpu0.
946		 */
947		ia64_set_kr(IA64_KR_PER_CPU_DATA,
948			    ia64_tpa(cpu_data) - (long) __per_cpu_start);
949	}
950#endif
951
952	get_cache_info();
953
954	/*
955	 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
956	 * ia64_mmu_init() yet.  And we can't call ia64_mmu_init() first because it
957	 * depends on the data returned by identify_cpu().  We break the dependency by
958	 * accessing cpu_data() through the canonical per-CPU address.
959	 */
960	cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(ia64_cpu_info) - __per_cpu_start);
961	identify_cpu(cpu_info);
962
963#ifdef CONFIG_MCKINLEY
964	{
965#		define FEATURE_SET 16
966		struct ia64_pal_retval iprv;
967
968		if (cpu_info->family == 0x1f) {
969			PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
970			if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
971				PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
972				              (iprv.v1 | 0x80), FEATURE_SET, 0);
973		}
974	}
975#endif
976
977	/* Clear the stack memory reserved for pt_regs: */
978	memset(task_pt_regs(current), 0, sizeof(struct pt_regs));
979
980	ia64_set_kr(IA64_KR_FPU_OWNER, 0);
981
982	/*
983	 * Initialize the page-table base register to a global
984	 * directory with all zeroes.  This ensure that we can handle
985	 * TLB-misses to user address-space even before we created the
986	 * first user address-space.  This may happen, e.g., due to
987	 * aggressive use of lfetch.fault.
988	 */
989	ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
990
991	/*
992	 * Initialize default control register to defer speculative faults except
993	 * for those arising from TLB misses, which are not deferred.  The
994	 * kernel MUST NOT depend on a particular setting of these bits (in other words,
995	 * the kernel must have recovery code for all speculative accesses).  Turn on
996	 * dcr.lc as per recommendation by the architecture team.  Most IA-32 apps
997	 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
998	 * be fine).
999	 */
1000	ia64_setreg(_IA64_REG_CR_DCR,  (  IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
1001					| IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
1002	atomic_inc(&init_mm.mm_count);
1003	current->active_mm = &init_mm;
1004	BUG_ON(current->mm);
1005
1006	ia64_mmu_init(ia64_imva(cpu_data));
1007	ia64_mca_cpu_init(ia64_imva(cpu_data));
1008
1009	/* Clear ITC to eliminate sched_clock() overflows in human time.  */
1010	ia64_set_itc(0);
1011
1012	/* disable all local interrupt sources: */
1013	ia64_set_itv(1 << 16);
1014	ia64_set_lrr0(1 << 16);
1015	ia64_set_lrr1(1 << 16);
1016	ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
1017	ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
1018
1019	/* clear TPR & XTP to enable all interrupt classes: */
1020	ia64_setreg(_IA64_REG_CR_TPR, 0);
1021
1022	/* Clear any pending interrupts left by SAL/EFI */
1023	while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR)
1024		ia64_eoi();
1025
1026#ifdef CONFIG_SMP
1027	normal_xtp();
1028#endif
1029
1030	/* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
1031	if (ia64_pal_vm_summary(NULL, &vmi) == 0) {
1032		max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
1033		setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, NPTCG_FROM_PAL);
1034	} else {
1035		printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
1036		max_ctx = (1U << 15) - 1;	/* use architected minimum */
1037	}
1038	while (max_ctx < ia64_ctx.max_ctx) {
1039		unsigned int old = ia64_ctx.max_ctx;
1040		if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
1041			break;
1042	}
1043
1044	if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
1045		printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
1046		       "stacked regs\n");
1047		num_phys_stacked = 96;
1048	}
1049	/* size of physical stacked register partition plus 8 bytes: */
1050	if (num_phys_stacked > max_num_phys_stacked) {
1051		ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8);
1052		max_num_phys_stacked = num_phys_stacked;
1053	}
1054	platform_cpu_init();
1055}
1056
1057void __init
1058check_bugs (void)
1059{
1060	ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
1061			       (unsigned long) __end___mckinley_e9_bundles);
1062}
1063
1064static int __init run_dmi_scan(void)
1065{
1066	dmi_scan_machine();
1067	dmi_memdev_walk();
1068	dmi_set_dump_stack_arch_desc();
1069	return 0;
1070}
1071core_initcall(run_dmi_scan);
1072