1/* spr-regs.h: special-purpose registers on the FRV 2 * 3 * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved. 4 * Written by David Howells (dhowells@redhat.com) 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12#ifndef _ASM_SPR_REGS_H 13#define _ASM_SPR_REGS_H 14 15/* 16 * PSR - Processor Status Register 17 */ 18#define PSR_ET 0x00000001 /* enable interrupts/exceptions flag */ 19#define PSR_PS 0x00000002 /* previous supervisor mode flag */ 20#define PSR_S 0x00000004 /* supervisor mode flag */ 21#define PSR_PIL 0x00000078 /* processor external interrupt level */ 22#define PSR_PIL_0 0x00000000 /* - no interrupt in progress */ 23#define PSR_PIL_13 0x00000068 /* - debugging only */ 24#define PSR_PIL_14 0x00000070 /* - debugging in progress */ 25#define PSR_PIL_15 0x00000078 /* - NMI in progress */ 26#define PSR_EM 0x00000080 /* enable media operation */ 27#define PSR_EF 0x00000100 /* enable FPU operation */ 28#define PSR_BE 0x00001000 /* endianness mode */ 29#define PSR_BE_LE 0x00000000 /* - little endian mode */ 30#define PSR_BE_BE 0x00001000 /* - big endian mode */ 31#define PSR_CM 0x00002000 /* conditional mode */ 32#define PSR_NEM 0x00004000 /* non-excepting mode */ 33#define PSR_ICE 0x00010000 /* in-circuit emulation mode */ 34#define PSR_VERSION_SHIFT 24 /* CPU silicon ID */ 35#define PSR_IMPLE_SHIFT 28 /* CPU core ID */ 36 37#define PSR_VERSION(psr) (((psr) >> PSR_VERSION_SHIFT) & 0xf) 38#define PSR_IMPLE(psr) (((psr) >> PSR_IMPLE_SHIFT) & 0xf) 39 40#define PSR_IMPLE_FR401 0x2 41#define PSR_VERSION_FR401_MB93401 0x0 42#define PSR_VERSION_FR401_MB93401A 0x1 43#define PSR_VERSION_FR401_MB93403 0x2 44 45#define PSR_IMPLE_FR405 0x4 46#define PSR_VERSION_FR405_MB93405 0x0 47 48#define PSR_IMPLE_FR451 0x5 49#define PSR_VERSION_FR451_MB93451 0x0 50 51#define PSR_IMPLE_FR501 0x1 52#define PSR_VERSION_FR501_MB93501 0x1 53#define PSR_VERSION_FR501_MB93501A 0x2 54 55#define PSR_IMPLE_FR551 0x3 56#define PSR_VERSION_FR551_MB93555 0x1 57 58#define __get_PSR() ({ unsigned long x; asm volatile("movsg psr,%0" : "=r"(x)); x; }) 59#define __set_PSR(V) do { asm volatile("movgs %0,psr" : : "r"(V)); } while(0) 60 61/* 62 * TBR - Trap Base Register 63 */ 64#define TBR_TT 0x00000ff0 65#define TBR_TT_INSTR_MMU_MISS (0x01 << 4) 66#define TBR_TT_INSTR_ACC_ERROR (0x02 << 4) 67#define TBR_TT_INSTR_ACC_EXCEP (0x03 << 4) 68#define TBR_TT_PRIV_INSTR (0x06 << 4) 69#define TBR_TT_ILLEGAL_INSTR (0x07 << 4) 70#define TBR_TT_FP_EXCEPTION (0x0d << 4) 71#define TBR_TT_MP_EXCEPTION (0x0e << 4) 72#define TBR_TT_DATA_ACC_ERROR (0x11 << 4) 73#define TBR_TT_DATA_MMU_MISS (0x12 << 4) 74#define TBR_TT_DATA_ACC_EXCEP (0x13 << 4) 75#define TBR_TT_DATA_STR_ERROR (0x14 << 4) 76#define TBR_TT_DIVISION_EXCEP (0x17 << 4) 77#define TBR_TT_COMMIT_EXCEP (0x19 << 4) 78#define TBR_TT_INSTR_TLB_MISS (0x1a << 4) 79#define TBR_TT_DATA_TLB_MISS (0x1b << 4) 80#define TBR_TT_DATA_DAT_EXCEP (0x1d << 4) 81#define TBR_TT_DECREMENT_TIMER (0x1f << 4) 82#define TBR_TT_COMPOUND_EXCEP (0x20 << 4) 83#define TBR_TT_INTERRUPT_1 (0x21 << 4) 84#define TBR_TT_INTERRUPT_2 (0x22 << 4) 85#define TBR_TT_INTERRUPT_3 (0x23 << 4) 86#define TBR_TT_INTERRUPT_4 (0x24 << 4) 87#define TBR_TT_INTERRUPT_5 (0x25 << 4) 88#define TBR_TT_INTERRUPT_6 (0x26 << 4) 89#define TBR_TT_INTERRUPT_7 (0x27 << 4) 90#define TBR_TT_INTERRUPT_8 (0x28 << 4) 91#define TBR_TT_INTERRUPT_9 (0x29 << 4) 92#define TBR_TT_INTERRUPT_10 (0x2a << 4) 93#define TBR_TT_INTERRUPT_11 (0x2b << 4) 94#define TBR_TT_INTERRUPT_12 (0x2c << 4) 95#define TBR_TT_INTERRUPT_13 (0x2d << 4) 96#define TBR_TT_INTERRUPT_14 (0x2e << 4) 97#define TBR_TT_INTERRUPT_15 (0x2f << 4) 98#define TBR_TT_TRAP0 (0x80 << 4) 99#define TBR_TT_TRAP1 (0x81 << 4) 100#define TBR_TT_TRAP2 (0x82 << 4) 101#define TBR_TT_TRAP3 (0x83 << 4) 102#define TBR_TT_TRAP120 (0xf8 << 4) 103#define TBR_TT_TRAP121 (0xf9 << 4) 104#define TBR_TT_TRAP122 (0xfa << 4) 105#define TBR_TT_TRAP123 (0xfb << 4) 106#define TBR_TT_TRAP124 (0xfc << 4) 107#define TBR_TT_TRAP125 (0xfd << 4) 108#define TBR_TT_TRAP126 (0xfe << 4) 109#define TBR_TT_BREAK (0xff << 4) 110 111#define TBR_TT_ATOMIC_CMPXCHG32 TBR_TT_TRAP120 112#define TBR_TT_ATOMIC_XCHG32 TBR_TT_TRAP121 113#define TBR_TT_ATOMIC_XOR TBR_TT_TRAP122 114#define TBR_TT_ATOMIC_OR TBR_TT_TRAP123 115#define TBR_TT_ATOMIC_AND TBR_TT_TRAP124 116#define TBR_TT_ATOMIC_SUB TBR_TT_TRAP125 117#define TBR_TT_ATOMIC_ADD TBR_TT_TRAP126 118 119#define __get_TBR() ({ unsigned long x; asm volatile("movsg tbr,%0" : "=r"(x)); x; }) 120 121/* 122 * HSR0 - Hardware Status Register 0 123 */ 124#define HSR0_PDM 0x00000007 /* power down mode */ 125#define HSR0_PDM_NORMAL 0x00000000 /* - normal mode */ 126#define HSR0_PDM_CORE_SLEEP 0x00000001 /* - CPU core sleep mode */ 127#define HSR0_PDM_BUS_SLEEP 0x00000003 /* - bus sleep mode */ 128#define HSR0_PDM_PLL_RUN 0x00000005 /* - PLL run */ 129#define HSR0_PDM_PLL_STOP 0x00000007 /* - PLL stop */ 130#define HSR0_GRLE 0x00000040 /* GR lower register set enable */ 131#define HSR0_GRHE 0x00000080 /* GR higher register set enable */ 132#define HSR0_FRLE 0x00000100 /* FR lower register set enable */ 133#define HSR0_FRHE 0x00000200 /* FR higher register set enable */ 134#define HSR0_GRN 0x00000400 /* GR quantity */ 135#define HSR0_GRN_64 0x00000000 /* - 64 GR registers */ 136#define HSR0_GRN_32 0x00000400 /* - 32 GR registers */ 137#define HSR0_FRN 0x00000800 /* FR quantity */ 138#define HSR0_FRN_64 0x00000000 /* - 64 FR registers */ 139#define HSR0_FRN_32 0x00000800 /* - 32 FR registers */ 140#define HSR0_SA 0x00001000 /* start address (RAMBOOT#) */ 141#define HSR0_ETMI 0x00008000 /* enable TIMERI (64-bit up timer) */ 142#define HSR0_ETMD 0x00004000 /* enable TIMERD (32-bit down timer) */ 143#define HSR0_PEDAT 0x00010000 /* previous DAT mode */ 144#define HSR0_XEDAT 0x00020000 /* exception DAT mode */ 145#define HSR0_EDAT 0x00080000 /* enable DAT mode */ 146#define HSR0_RME 0x00400000 /* enable RAM mode */ 147#define HSR0_EMEM 0x00800000 /* enable MMU_Miss mask */ 148#define HSR0_EXMMU 0x01000000 /* enable extended MMU mode */ 149#define HSR0_EDMMU 0x02000000 /* enable data MMU */ 150#define HSR0_EIMMU 0x04000000 /* enable instruction MMU */ 151#define HSR0_CBM 0x08000000 /* copy back mode */ 152#define HSR0_CBM_WRITE_THRU 0x00000000 /* - write through */ 153#define HSR0_CBM_COPY_BACK 0x08000000 /* - copy back */ 154#define HSR0_NWA 0x10000000 /* no write allocate */ 155#define HSR0_DCE 0x40000000 /* data cache enable */ 156#define HSR0_ICE 0x80000000 /* instruction cache enable */ 157 158#define __get_HSR(R) ({ unsigned long x; asm volatile("movsg hsr"#R",%0" : "=r"(x)); x; }) 159#define __set_HSR(R,V) do { asm volatile("movgs %0,hsr"#R : : "r"(V)); } while(0) 160 161/* 162 * CCR - Condition Codes Register 163 */ 164#define CCR_FCC0 0x0000000f /* FP/Media condition 0 (fcc0 reg) */ 165#define CCR_FCC1 0x000000f0 /* FP/Media condition 1 (fcc1 reg) */ 166#define CCR_FCC2 0x00000f00 /* FP/Media condition 2 (fcc2 reg) */ 167#define CCR_FCC3 0x0000f000 /* FP/Media condition 3 (fcc3 reg) */ 168#define CCR_ICC0 0x000f0000 /* Integer condition 0 (icc0 reg) */ 169#define CCR_ICC0_C 0x00010000 /* - Carry flag */ 170#define CCR_ICC0_V 0x00020000 /* - Overflow flag */ 171#define CCR_ICC0_Z 0x00040000 /* - Zero flag */ 172#define CCR_ICC0_N 0x00080000 /* - Negative flag */ 173#define CCR_ICC1 0x00f00000 /* Integer condition 1 (icc1 reg) */ 174#define CCR_ICC2 0x0f000000 /* Integer condition 2 (icc2 reg) */ 175#define CCR_ICC3 0xf0000000 /* Integer condition 3 (icc3 reg) */ 176 177/* 178 * CCCR - Condition Codes for Conditional Instructions Register 179 */ 180#define CCCR_CC0 0x00000003 /* condition 0 (cc0 reg) */ 181#define CCCR_CC0_FALSE 0x00000002 /* - condition is false */ 182#define CCCR_CC0_TRUE 0x00000003 /* - condition is true */ 183#define CCCR_CC1 0x0000000c /* condition 1 (cc1 reg) */ 184#define CCCR_CC2 0x00000030 /* condition 2 (cc2 reg) */ 185#define CCCR_CC3 0x000000c0 /* condition 3 (cc3 reg) */ 186#define CCCR_CC4 0x00000300 /* condition 4 (cc4 reg) */ 187#define CCCR_CC5 0x00000c00 /* condition 5 (cc5 reg) */ 188#define CCCR_CC6 0x00003000 /* condition 6 (cc6 reg) */ 189#define CCCR_CC7 0x0000c000 /* condition 7 (cc7 reg) */ 190 191/* 192 * ISR - Integer Status Register 193 */ 194#define ISR_EMAM 0x00000001 /* memory misaligned access handling */ 195#define ISR_EMAM_EXCEPTION 0x00000000 /* - generate exception */ 196#define ISR_EMAM_FUDGE 0x00000001 /* - mask out invalid address bits */ 197#define ISR_AEXC 0x00000004 /* accrued [overflow] exception */ 198#define ISR_DTT 0x00000018 /* division type trap */ 199#define ISR_DTT_IGNORE 0x00000000 /* - ignore division error */ 200#define ISR_DTT_DIVBYZERO 0x00000008 /* - generate exception */ 201#define ISR_DTT_OVERFLOW 0x00000010 /* - record overflow */ 202#define ISR_EDE 0x00000020 /* enable division exception */ 203#define ISR_PLI 0x20000000 /* pre-load instruction information */ 204#define ISR_QI 0x80000000 /* quad data implementation information */ 205 206/* 207 * EPCR0 - Exception PC Register 208 */ 209#define EPCR0_V 0x00000001 /* register content validity indicator */ 210#define EPCR0_PC 0xfffffffc /* faulting instruction address */ 211 212/* 213 * ESR0/14/15 - Exception Status Register 214 */ 215#define ESRx_VALID 0x00000001 /* register content validity indicator */ 216#define ESRx_EC 0x0000003e /* exception type */ 217#define ESRx_EC_DATA_STORE 0x00000000 /* - data_store_error */ 218#define ESRx_EC_INSN_ACCESS 0x00000006 /* - instruction_access_error */ 219#define ESRx_EC_PRIV_INSN 0x00000008 /* - privileged_instruction */ 220#define ESRx_EC_ILL_INSN 0x0000000a /* - illegal_instruction */ 221#define ESRx_EC_MP_EXCEP 0x0000001c /* - mp_exception */ 222#define ESRx_EC_DATA_ACCESS 0x00000020 /* - data_access_error */ 223#define ESRx_EC_DIVISION 0x00000026 /* - division_exception */ 224#define ESRx_EC_ITLB_MISS 0x00000034 /* - instruction_access_TLB_miss */ 225#define ESRx_EC_DTLB_MISS 0x00000036 /* - data_access_TLB_miss */ 226#define ESRx_EC_DATA_ACCESS_DAT 0x0000003a /* - data_access_DAT_exception */ 227 228#define ESR0_IAEC 0x00000100 /* info for instruction-access-exception */ 229#define ESR0_IAEC_RESV 0x00000000 /* - reserved */ 230#define ESR0_IAEC_PROT_VIOL 0x00000100 /* - protection violation */ 231 232#define ESR0_ATXC 0x00f00000 /* address translation exception code */ 233#define ESR0_ATXC_MMU_MISS 0x00000000 /* - MMU miss exception and more (?) */ 234#define ESR0_ATXC_MULTI_DAT 0x00800000 /* - multiple DAT entry hit */ 235#define ESR0_ATXC_MULTI_SAT 0x00900000 /* - multiple SAT entry hit */ 236#define ESR0_ATXC_AMRTLB_MISS 0x00a00000 /* - MMU/TLB miss exception */ 237#define ESR0_ATXC_PRIV_EXCEP 0x00c00000 /* - privilege protection fault */ 238#define ESR0_ATXC_WP_EXCEP 0x00d00000 /* - write protection fault */ 239 240#define ESR0_EAV 0x00000800 /* true if EAR0 register valid */ 241#define ESR15_EAV 0x00000800 /* true if EAR15 register valid */ 242 243/* 244 * ESFR1 - Exception Status Valid Flag Register 245 */ 246#define ESFR1_ESR0 0x00000001 /* true if ESR0 is valid */ 247#define ESFR1_ESR14 0x00004000 /* true if ESR14 is valid */ 248#define ESFR1_ESR15 0x00008000 /* true if ESR15 is valid */ 249 250/* 251 * MSR - Media Status Register 252 */ 253#define MSR0_AOVF 0x00000001 /* overflow exception accrued */ 254#define MSRx_OVF 0x00000002 /* overflow exception detected */ 255#define MSRx_SIE 0x0000003c /* last SIMD instruction exception detected */ 256#define MSRx_SIE_NONE 0x00000000 /* - none detected */ 257#define MSRx_SIE_FRkHI_ACCk 0x00000020 /* - exception at FRkHI or ACCk */ 258#define MSRx_SIE_FRkLO_ACCk1 0x00000010 /* - exception at FRkLO or ACCk+1 */ 259#define MSRx_SIE_FRk1HI_ACCk2 0x00000008 /* - exception at FRk+1HI or ACCk+2 */ 260#define MSRx_SIE_FRk1LO_ACCk3 0x00000004 /* - exception at FRk+1LO or ACCk+3 */ 261#define MSR0_MTT 0x00007000 /* type of last media trap detected */ 262#define MSR0_MTT_NONE 0x00000000 /* - none detected */ 263#define MSR0_MTT_OVERFLOW 0x00001000 /* - overflow detected */ 264#define MSR0_HI 0x00c00000 /* hardware implementation */ 265#define MSR0_HI_ROUNDING 0x00000000 /* - rounding mode */ 266#define MSR0_HI_NONROUNDING 0x00c00000 /* - non-rounding mode */ 267#define MSR0_EMCI 0x01000000 /* enable media custom instructions */ 268#define MSR0_SRDAV 0x10000000 /* select rounding mode of MAVEH */ 269#define MSR0_SRDAV_RDAV 0x00000000 /* - controlled by MSR.RDAV */ 270#define MSR0_SRDAV_RD 0x10000000 /* - controlled by MSR.RD */ 271#define MSR0_RDAV 0x20000000 /* rounding mode of MAVEH */ 272#define MSR0_RDAV_NEAREST_MI 0x00000000 /* - round to nearest minus */ 273#define MSR0_RDAV_NEAREST_PL 0x20000000 /* - round to nearest plus */ 274#define MSR0_RD 0xc0000000 /* rounding mode */ 275#define MSR0_RD_NEAREST 0x00000000 /* - nearest */ 276#define MSR0_RD_ZERO 0x40000000 /* - zero */ 277#define MSR0_RD_POS_INF 0x80000000 /* - positive infinity */ 278#define MSR0_RD_NEG_INF 0xc0000000 /* - negative infinity */ 279 280/* 281 * IAMPR0-7 - Instruction Address Mapping Register 282 * DAMPR0-7 - Data Address Mapping Register 283 */ 284#define xAMPRx_V 0x00000001 /* register content validity indicator */ 285#define DAMPRx_WP 0x00000002 /* write protect */ 286#define DAMPRx_WP_RW 0x00000000 /* - read/write */ 287#define DAMPRx_WP_RO 0x00000002 /* - read-only */ 288#define xAMPRx_C 0x00000004 /* cached/uncached */ 289#define xAMPRx_C_CACHED 0x00000000 /* - cached */ 290#define xAMPRx_C_UNCACHED 0x00000004 /* - uncached */ 291#define xAMPRx_S 0x00000008 /* supervisor only */ 292#define xAMPRx_S_USER 0x00000000 /* - userspace can access */ 293#define xAMPRx_S_KERNEL 0x00000008 /* - kernel only */ 294#define xAMPRx_SS 0x000000f0 /* segment size */ 295#define xAMPRx_SS_16Kb 0x00000000 /* - 16 kilobytes */ 296#define xAMPRx_SS_64Kb 0x00000010 /* - 64 kilobytes */ 297#define xAMPRx_SS_256Kb 0x00000020 /* - 256 kilobytes */ 298#define xAMPRx_SS_1Mb 0x00000030 /* - 1 megabyte */ 299#define xAMPRx_SS_2Mb 0x00000040 /* - 2 megabytes */ 300#define xAMPRx_SS_4Mb 0x00000050 /* - 4 megabytes */ 301#define xAMPRx_SS_8Mb 0x00000060 /* - 8 megabytes */ 302#define xAMPRx_SS_16Mb 0x00000070 /* - 16 megabytes */ 303#define xAMPRx_SS_32Mb 0x00000080 /* - 32 megabytes */ 304#define xAMPRx_SS_64Mb 0x00000090 /* - 64 megabytes */ 305#define xAMPRx_SS_128Mb 0x000000a0 /* - 128 megabytes */ 306#define xAMPRx_SS_256Mb 0x000000b0 /* - 256 megabytes */ 307#define xAMPRx_SS_512Mb 0x000000c0 /* - 512 megabytes */ 308#define xAMPRx_RESERVED8 0x00000100 /* reserved bit */ 309#define xAMPRx_NG 0x00000200 /* non-global */ 310#define xAMPRx_L 0x00000400 /* locked */ 311#define xAMPRx_M 0x00000800 /* modified */ 312#define xAMPRx_D 0x00001000 /* DAT entry */ 313#define xAMPRx_RESERVED13 0x00002000 /* reserved bit */ 314#define xAMPRx_PPFN 0xfff00000 /* physical page frame number */ 315 316#define xAMPRx_V_BIT 0 317#define DAMPRx_WP_BIT 1 318#define xAMPRx_C_BIT 2 319#define xAMPRx_S_BIT 3 320#define xAMPRx_RESERVED8_BIT 8 321#define xAMPRx_NG_BIT 9 322#define xAMPRx_L_BIT 10 323#define xAMPRx_M_BIT 11 324#define xAMPRx_D_BIT 12 325#define xAMPRx_RESERVED13_BIT 13 326 327#define __get_IAMPR(R) ({ unsigned long x; asm volatile("movsg iampr"#R",%0" : "=r"(x)); x; }) 328#define __get_DAMPR(R) ({ unsigned long x; asm volatile("movsg dampr"#R",%0" : "=r"(x)); x; }) 329 330#define __get_IAMLR(R) ({ unsigned long x; asm volatile("movsg iamlr"#R",%0" : "=r"(x)); x; }) 331#define __get_DAMLR(R) ({ unsigned long x; asm volatile("movsg damlr"#R",%0" : "=r"(x)); x; }) 332 333#define __set_IAMPR(R,V) do { asm volatile("movgs %0,iampr"#R : : "r"(V)); } while(0) 334#define __set_DAMPR(R,V) do { asm volatile("movgs %0,dampr"#R : : "r"(V)); } while(0) 335 336#define __set_IAMLR(R,V) do { asm volatile("movgs %0,iamlr"#R : : "r"(V)); } while(0) 337#define __set_DAMLR(R,V) do { asm volatile("movgs %0,damlr"#R : : "r"(V)); } while(0) 338 339#define save_dampr(R, _dampr) \ 340do { \ 341 asm volatile("movsg dampr"R",%0" : "=r"(_dampr)); \ 342} while(0) 343 344#define restore_dampr(R, _dampr) \ 345do { \ 346 asm volatile("movgs %0,dampr"R :: "r"(_dampr)); \ 347} while(0) 348 349/* 350 * AMCR - Address Mapping Control Register 351 */ 352#define AMCR_IAMRN 0x000000ff /* quantity of IAMPR registers */ 353#define AMCR_DAMRN 0x0000ff00 /* quantity of DAMPR registers */ 354 355/* 356 * TTBR - Address Translation Table Base Register 357 */ 358#define __get_TTBR() ({ unsigned long x; asm volatile("movsg ttbr,%0" : "=r"(x)); x; }) 359 360/* 361 * TPXR - TLB Probe Extend Register 362 */ 363#define TPXR_E 0x00000001 364#define TPXR_LMAX_SHIFT 20 365#define TPXR_LMAX_SMASK 0xf 366#define TPXR_WMAX_SHIFT 24 367#define TPXR_WMAX_SMASK 0xf 368#define TPXR_WAY_SHIFT 28 369#define TPXR_WAY_SMASK 0xf 370 371/* 372 * DCR - Debug Control Register 373 */ 374#define DCR_IBCE3 0x00000001 /* break on conditional insn pointed to by IBAR3 */ 375#define DCR_IBE3 0x00000002 /* break on insn pointed to by IBAR3 */ 376#define DCR_IBCE1 0x00000004 /* break on conditional insn pointed to by IBAR2 */ 377#define DCR_IBE1 0x00000008 /* break on insn pointed to by IBAR2 */ 378#define DCR_IBCE2 0x00000010 /* break on conditional insn pointed to by IBAR1 */ 379#define DCR_IBE2 0x00000020 /* break on insn pointed to by IBAR1 */ 380#define DCR_IBCE0 0x00000040 /* break on conditional insn pointed to by IBAR0 */ 381#define DCR_IBE0 0x00000080 /* break on insn pointed to by IBAR0 */ 382 383#define DCR_DDBE1 0x00004000 /* use DBDR1x when checking DBAR1 */ 384#define DCR_DWBE1 0x00008000 /* break on store to address in DBAR1/DBMR1x */ 385#define DCR_DRBE1 0x00010000 /* break on load from address in DBAR1/DBMR1x */ 386#define DCR_DDBE0 0x00020000 /* use DBDR0x when checking DBAR0 */ 387#define DCR_DWBE0 0x00040000 /* break on store to address in DBAR0/DBMR0x */ 388#define DCR_DRBE0 0x00080000 /* break on load from address in DBAR0/DBMR0x */ 389 390#define DCR_EIM 0x0c000000 /* external interrupt disable */ 391#define DCR_IBM 0x10000000 /* instruction break disable */ 392#define DCR_SE 0x20000000 /* single step enable */ 393#define DCR_EBE 0x40000000 /* exception break enable */ 394 395/* 396 * BRR - Break Interrupt Request Register 397 */ 398#define BRR_ST 0x00000001 /* single-step detected */ 399#define BRR_SB 0x00000002 /* break instruction detected */ 400#define BRR_BB 0x00000004 /* branch with hint detected */ 401#define BRR_CBB 0x00000008 /* branch to LR detected */ 402#define BRR_IBx 0x000000f0 /* hardware breakpoint detected */ 403#define BRR_DBx 0x00000f00 /* hardware watchpoint detected */ 404#define BRR_DBNEx 0x0000f000 /* ? */ 405#define BRR_EBTT 0x00ff0000 /* trap type of exception break */ 406#define BRR_TB 0x10000000 /* external break request detected */ 407#define BRR_CB 0x20000000 /* ICE break command detected */ 408#define BRR_EB 0x40000000 /* exception break detected */ 409 410/* 411 * BPSR - Break PSR Save Register 412 */ 413#define BPSR_BET 0x00000001 /* former PSR.ET */ 414#define BPSR_BS 0x00001000 /* former PSR.S */ 415 416#endif /* _ASM_SPR_REGS_H */ 417