1/* 2 * Copyright 2007-2008 Analog Devices Inc. 3 * 4 * Licensed under the GPL-2 or later 5 */ 6 7#ifndef _BF527_IRQ_H_ 8#define _BF527_IRQ_H_ 9 10#include <mach-common/irq.h> 11 12#define NR_PERI_INTS (2 * 32) 13 14#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ 15#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */ 16#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */ 17#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */ 18#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */ 19#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */ 20#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */ 21#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */ 22#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */ 23#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */ 24#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */ 25#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */ 26#define IRQ_RTC BFIN_IRQ(14) /* RTC */ 27#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */ 28#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */ 29#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */ 30#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */ 31#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */ 32#define IRQ_TWI BFIN_IRQ(20) /* TWI */ 33#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */ 34#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */ 35#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */ 36#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */ 37#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */ 38#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */ 39#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */ 40#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */ 41#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */ 42#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ 43#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ 44#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */ 45#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */ 46#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */ 47#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */ 48#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */ 49#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */ 50#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */ 51#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */ 52#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */ 53#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */ 54#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */ 55#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */ 56#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */ 57#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */ 58#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */ 59#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */ 60#define IRQ_SPI_ERROR BFIN_IRQ(47) /* SPI Status */ 61#define IRQ_NFC_ERROR BFIN_IRQ(48) /* NAND Error */ 62#define IRQ_HDMA_ERROR BFIN_IRQ(49) /* HDMA Error */ 63#define IRQ_HDMA BFIN_IRQ(50) /* HDMA (TFI) */ 64#define IRQ_USB_EINT BFIN_IRQ(51) /* USB_EINT Interrupt */ 65#define IRQ_USB_INT0 BFIN_IRQ(52) /* USB_INT0 Interrupt */ 66#define IRQ_USB_INT1 BFIN_IRQ(53) /* USB_INT1 Interrupt */ 67#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */ 68#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */ 69 70#define SYS_IRQS BFIN_IRQ(63) /* 70 */ 71 72#define IRQ_PF0 71 73#define IRQ_PF1 72 74#define IRQ_PF2 73 75#define IRQ_PF3 74 76#define IRQ_PF4 75 77#define IRQ_PF5 76 78#define IRQ_PF6 77 79#define IRQ_PF7 78 80#define IRQ_PF8 79 81#define IRQ_PF9 80 82#define IRQ_PF10 81 83#define IRQ_PF11 82 84#define IRQ_PF12 83 85#define IRQ_PF13 84 86#define IRQ_PF14 85 87#define IRQ_PF15 86 88 89#define IRQ_PG0 87 90#define IRQ_PG1 88 91#define IRQ_PG2 89 92#define IRQ_PG3 90 93#define IRQ_PG4 91 94#define IRQ_PG5 92 95#define IRQ_PG6 93 96#define IRQ_PG7 94 97#define IRQ_PG8 95 98#define IRQ_PG9 96 99#define IRQ_PG10 97 100#define IRQ_PG11 98 101#define IRQ_PG12 99 102#define IRQ_PG13 100 103#define IRQ_PG14 101 104#define IRQ_PG15 102 105 106#define IRQ_PH0 103 107#define IRQ_PH1 104 108#define IRQ_PH2 105 109#define IRQ_PH3 106 110#define IRQ_PH4 107 111#define IRQ_PH5 108 112#define IRQ_PH6 109 113#define IRQ_PH7 110 114#define IRQ_PH8 111 115#define IRQ_PH9 112 116#define IRQ_PH10 113 117#define IRQ_PH11 114 118#define IRQ_PH12 115 119#define IRQ_PH13 116 120#define IRQ_PH14 117 121#define IRQ_PH15 118 122 123#define GPIO_IRQ_BASE IRQ_PF0 124 125#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */ 126#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */ 127#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */ 128#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */ 129#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */ 130#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */ 131#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */ 132#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */ 133 134#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1) 135 136/* IAR0 BIT FIELDS */ 137#define IRQ_PLL_WAKEUP_POS 0 138#define IRQ_DMA0_ERROR_POS 4 139#define IRQ_DMAR0_BLK_POS 8 140#define IRQ_DMAR1_BLK_POS 12 141#define IRQ_DMAR0_OVR_POS 16 142#define IRQ_DMAR1_OVR_POS 20 143#define IRQ_PPI_ERROR_POS 24 144#define IRQ_MAC_ERROR_POS 28 145 146/* IAR1 BIT FIELDS */ 147#define IRQ_SPORT0_ERROR_POS 0 148#define IRQ_SPORT1_ERROR_POS 4 149#define IRQ_UART0_ERROR_POS 16 150#define IRQ_UART1_ERROR_POS 20 151#define IRQ_RTC_POS 24 152#define IRQ_PPI_POS 28 153 154/* IAR2 BIT FIELDS */ 155#define IRQ_SPORT0_RX_POS 0 156#define IRQ_SPORT0_TX_POS 4 157#define IRQ_SPORT1_RX_POS 8 158#define IRQ_SPORT1_TX_POS 12 159#define IRQ_TWI_POS 16 160#define IRQ_SPI_POS 20 161#define IRQ_UART0_RX_POS 24 162#define IRQ_UART0_TX_POS 28 163 164/* IAR3 BIT FIELDS */ 165#define IRQ_UART1_RX_POS 0 166#define IRQ_UART1_TX_POS 4 167#define IRQ_OPTSEC_POS 8 168#define IRQ_CNT_POS 12 169#define IRQ_MAC_RX_POS 16 170#define IRQ_PORTH_INTA_POS 20 171#define IRQ_MAC_TX_POS 24 172#define IRQ_PORTH_INTB_POS 28 173 174/* IAR4 BIT FIELDS */ 175#define IRQ_TIMER0_POS 0 176#define IRQ_TIMER1_POS 4 177#define IRQ_TIMER2_POS 8 178#define IRQ_TIMER3_POS 12 179#define IRQ_TIMER4_POS 16 180#define IRQ_TIMER5_POS 20 181#define IRQ_TIMER6_POS 24 182#define IRQ_TIMER7_POS 28 183 184/* IAR5 BIT FIELDS */ 185#define IRQ_PORTG_INTA_POS 0 186#define IRQ_PORTG_INTB_POS 4 187#define IRQ_MEM_DMA0_POS 8 188#define IRQ_MEM_DMA1_POS 12 189#define IRQ_WATCH_POS 16 190#define IRQ_PORTF_INTA_POS 20 191#define IRQ_PORTF_INTB_POS 24 192#define IRQ_SPI_ERROR_POS 28 193 194/* IAR6 BIT FIELDS */ 195#define IRQ_NFC_ERROR_POS 0 196#define IRQ_HDMA_ERROR_POS 4 197#define IRQ_HDMA_POS 8 198#define IRQ_USB_EINT_POS 12 199#define IRQ_USB_INT0_POS 16 200#define IRQ_USB_INT1_POS 20 201#define IRQ_USB_INT2_POS 24 202#define IRQ_USB_DMA_POS 28 203 204#endif 205