1/* 2 * Blackfin low-level cache routines 3 * 4 * Copyright 2004-2009 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2 or later. 7 */ 8 9#ifndef _BLACKFIN_CACHEFLUSH_H 10#define _BLACKFIN_CACHEFLUSH_H 11 12#include <asm/blackfin.h> /* for SSYNC() */ 13#include <asm/sections.h> /* for _ramend */ 14#ifdef CONFIG_SMP 15#include <asm/smp.h> 16#endif 17 18extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address); 19extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address); 20extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address); 21extern void blackfin_dflush_page(void *page); 22extern void blackfin_invalidate_entire_dcache(void); 23extern void blackfin_invalidate_entire_icache(void); 24 25#define flush_dcache_mmap_lock(mapping) do { } while (0) 26#define flush_dcache_mmap_unlock(mapping) do { } while (0) 27#define flush_cache_mm(mm) do { } while (0) 28#define flush_cache_range(vma, start, end) do { } while (0) 29#define flush_cache_page(vma, vmaddr) do { } while (0) 30#define flush_cache_vmap(start, end) do { } while (0) 31#define flush_cache_vunmap(start, end) do { } while (0) 32 33#ifdef CONFIG_SMP 34#define flush_icache_range_others(start, end) \ 35 smp_icache_flush_range_others((start), (end)) 36#else 37#define flush_icache_range_others(start, end) do { } while (0) 38#endif 39 40static inline void flush_icache_range(unsigned start, unsigned end) 41{ 42#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) 43 if (end <= physical_mem_end) 44 blackfin_dcache_flush_range(start, end); 45#endif 46#if defined(CONFIG_BFIN_L2_WRITEBACK) 47 if (start >= L2_START && end <= L2_START + L2_LENGTH) 48 blackfin_dcache_flush_range(start, end); 49#endif 50 51 /* Make sure all write buffers in the data side of the core 52 * are flushed before trying to invalidate the icache. This 53 * needs to be after the data flush and before the icache 54 * flush so that the SSYNC does the right thing in preventing 55 * the instruction prefetcher from hitting things in cached 56 * memory at the wrong time -- it runs much further ahead than 57 * the pipeline. 58 */ 59 SSYNC(); 60#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) 61 if (end <= physical_mem_end) { 62 blackfin_icache_flush_range(start, end); 63 flush_icache_range_others(start, end); 64 } 65#endif 66#if defined(CONFIG_BFIN_L2_ICACHEABLE) 67 if (start >= L2_START && end <= L2_START + L2_LENGTH) { 68 blackfin_icache_flush_range(start, end); 69 flush_icache_range_others(start, end); 70 } 71#endif 72} 73 74#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ 75do { memcpy(dst, src, len); \ 76 flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \ 77} while (0) 78 79#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len) 80 81#if defined(CONFIG_BFIN_DCACHE) 82# define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end)) 83#else 84# define invalidate_dcache_range(start,end) do { } while (0) 85#endif 86#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) 87# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end)) 88#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 89# define flush_dcache_page(page) blackfin_dflush_page(page_address(page)) 90#else 91# define flush_dcache_range(start,end) do { } while (0) 92#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 93# define flush_dcache_page(page) do { } while (0) 94#endif 95 96extern unsigned long reserved_mem_dcache_on; 97extern unsigned long reserved_mem_icache_on; 98 99static inline int bfin_addr_dcacheable(unsigned long addr) 100{ 101#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE 102 if (addr < (_ramend - DMA_UNCACHED_REGION)) 103 return 1; 104#endif 105 106 if (reserved_mem_dcache_on && 107 addr >= _ramend && addr < physical_mem_end) 108 return 1; 109 110#ifdef CONFIG_BFIN_L2_DCACHEABLE 111 if (addr >= L2_START && addr < L2_START + L2_LENGTH) 112 return 1; 113#endif 114 115 return 0; 116} 117 118#endif /* _BLACKFIN_ICACHEFLUSH_H */ 119