1/* 2 * sh73a0 processor support 3 * 4 * Copyright (C) 2010 Takashi Yoshii 5 * Copyright (C) 2010 Magnus Damm 6 * Copyright (C) 2008 Yoshihiro Shimoda 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; version 2 of the License. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17#include <linux/kernel.h> 18#include <linux/init.h> 19#include <linux/interrupt.h> 20#include <linux/irq.h> 21#include <linux/platform_device.h> 22#include <linux/of_platform.h> 23#include <linux/delay.h> 24#include <linux/input.h> 25#include <linux/i2c/i2c-sh_mobile.h> 26#include <linux/io.h> 27#include <linux/serial_sci.h> 28#include <linux/sh_dma.h> 29#include <linux/sh_timer.h> 30#include <linux/platform_data/sh_ipmmu.h> 31#include <linux/platform_data/irq-renesas-intc-irqpin.h> 32 33#include <asm/hardware/cache-l2x0.h> 34#include <asm/mach-types.h> 35#include <asm/mach/map.h> 36#include <asm/mach/arch.h> 37#include <asm/mach/time.h> 38 39#include "common.h" 40#include "dma-register.h" 41#include "intc.h" 42#include "irqs.h" 43#include "sh73a0.h" 44 45static struct map_desc sh73a0_io_desc[] __initdata = { 46 /* create a 1:1 identity mapping for 0xe6xxxxxx 47 * used by CPGA, INTC and PFC. 48 */ 49 { 50 .virtual = 0xe6000000, 51 .pfn = __phys_to_pfn(0xe6000000), 52 .length = 256 << 20, 53 .type = MT_DEVICE_NONSHARED 54 }, 55}; 56 57void __init sh73a0_map_io(void) 58{ 59 debug_ll_io_init(); 60 iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc)); 61} 62 63/* PFC */ 64static struct resource pfc_resources[] __initdata = { 65 DEFINE_RES_MEM(0xe6050000, 0x8000), 66 DEFINE_RES_MEM(0xe605801c, 0x000c), 67}; 68 69void __init sh73a0_pinmux_init(void) 70{ 71 platform_device_register_simple("pfc-sh73a0", -1, pfc_resources, 72 ARRAY_SIZE(pfc_resources)); 73} 74 75/* SCIF */ 76#define SH73A0_SCIF(scif_type, index, baseaddr, irq) \ 77static struct plat_sci_port scif##index##_platform_data = { \ 78 .type = scif_type, \ 79 .flags = UPF_BOOT_AUTOCONF, \ 80 .scscr = SCSCR_RE | SCSCR_TE, \ 81}; \ 82 \ 83static struct resource scif##index##_resources[] = { \ 84 DEFINE_RES_MEM(baseaddr, 0x100), \ 85 DEFINE_RES_IRQ(irq), \ 86}; \ 87 \ 88static struct platform_device scif##index##_device = { \ 89 .name = "sh-sci", \ 90 .id = index, \ 91 .resource = scif##index##_resources, \ 92 .num_resources = ARRAY_SIZE(scif##index##_resources), \ 93 .dev = { \ 94 .platform_data = &scif##index##_platform_data, \ 95 }, \ 96} 97 98SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72)); 99SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73)); 100SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74)); 101SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75)); 102SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78)); 103SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79)); 104SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156)); 105SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143)); 106SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80)); 107 108static struct sh_timer_config cmt1_platform_data = { 109 .channels_mask = 0x3f, 110}; 111 112static struct resource cmt1_resources[] = { 113 DEFINE_RES_MEM(0xe6138000, 0x200), 114 DEFINE_RES_IRQ(gic_spi(65)), 115}; 116 117static struct platform_device cmt1_device = { 118 .name = "sh-cmt-48", 119 .id = 1, 120 .dev = { 121 .platform_data = &cmt1_platform_data, 122 }, 123 .resource = cmt1_resources, 124 .num_resources = ARRAY_SIZE(cmt1_resources), 125}; 126 127/* TMU */ 128static struct sh_timer_config tmu0_platform_data = { 129 .channels_mask = 7, 130}; 131 132static struct resource tmu0_resources[] = { 133 DEFINE_RES_MEM(0xfff60000, 0x2c), 134 DEFINE_RES_IRQ(intcs_evt2irq(0xe80)), 135 DEFINE_RES_IRQ(intcs_evt2irq(0xea0)), 136 DEFINE_RES_IRQ(intcs_evt2irq(0xec0)), 137}; 138 139static struct platform_device tmu0_device = { 140 .name = "sh-tmu", 141 .id = 0, 142 .dev = { 143 .platform_data = &tmu0_platform_data, 144 }, 145 .resource = tmu0_resources, 146 .num_resources = ARRAY_SIZE(tmu0_resources), 147}; 148 149static struct resource i2c0_resources[] = { 150 [0] = DEFINE_RES_MEM(0xe6820000, 0x426), 151 [1] = { 152 .start = gic_spi(167), 153 .end = gic_spi(170), 154 .flags = IORESOURCE_IRQ, 155 }, 156}; 157 158static struct resource i2c1_resources[] = { 159 [0] = DEFINE_RES_MEM(0xe6822000, 0x426), 160 [1] = { 161 .start = gic_spi(51), 162 .end = gic_spi(54), 163 .flags = IORESOURCE_IRQ, 164 }, 165}; 166 167static struct resource i2c2_resources[] = { 168 [0] = DEFINE_RES_MEM(0xe6824000, 0x426), 169 [1] = { 170 .start = gic_spi(171), 171 .end = gic_spi(174), 172 .flags = IORESOURCE_IRQ, 173 }, 174}; 175 176static struct resource i2c3_resources[] = { 177 [0] = DEFINE_RES_MEM(0xe6826000, 0x426), 178 [1] = { 179 .start = gic_spi(183), 180 .end = gic_spi(186), 181 .flags = IORESOURCE_IRQ, 182 }, 183}; 184 185static struct resource i2c4_resources[] = { 186 [0] = DEFINE_RES_MEM(0xe6828000, 0x426), 187 [1] = { 188 .start = gic_spi(187), 189 .end = gic_spi(190), 190 .flags = IORESOURCE_IRQ, 191 }, 192}; 193 194static struct i2c_sh_mobile_platform_data i2c_platform_data = { 195 .clks_per_count = 2, 196}; 197 198static struct platform_device i2c0_device = { 199 .name = "i2c-sh_mobile", 200 .id = 0, 201 .resource = i2c0_resources, 202 .num_resources = ARRAY_SIZE(i2c0_resources), 203 .dev = { 204 .platform_data = &i2c_platform_data, 205 }, 206}; 207 208static struct platform_device i2c1_device = { 209 .name = "i2c-sh_mobile", 210 .id = 1, 211 .resource = i2c1_resources, 212 .num_resources = ARRAY_SIZE(i2c1_resources), 213 .dev = { 214 .platform_data = &i2c_platform_data, 215 }, 216}; 217 218static struct platform_device i2c2_device = { 219 .name = "i2c-sh_mobile", 220 .id = 2, 221 .resource = i2c2_resources, 222 .num_resources = ARRAY_SIZE(i2c2_resources), 223 .dev = { 224 .platform_data = &i2c_platform_data, 225 }, 226}; 227 228static struct platform_device i2c3_device = { 229 .name = "i2c-sh_mobile", 230 .id = 3, 231 .resource = i2c3_resources, 232 .num_resources = ARRAY_SIZE(i2c3_resources), 233 .dev = { 234 .platform_data = &i2c_platform_data, 235 }, 236}; 237 238static struct platform_device i2c4_device = { 239 .name = "i2c-sh_mobile", 240 .id = 4, 241 .resource = i2c4_resources, 242 .num_resources = ARRAY_SIZE(i2c4_resources), 243 .dev = { 244 .platform_data = &i2c_platform_data, 245 }, 246}; 247 248static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = { 249 { 250 .slave_id = SHDMA_SLAVE_SCIF0_TX, 251 .addr = 0xe6c40020, 252 .chcr = CHCR_TX(XMIT_SZ_8BIT), 253 .mid_rid = 0x21, 254 }, { 255 .slave_id = SHDMA_SLAVE_SCIF0_RX, 256 .addr = 0xe6c40024, 257 .chcr = CHCR_RX(XMIT_SZ_8BIT), 258 .mid_rid = 0x22, 259 }, { 260 .slave_id = SHDMA_SLAVE_SCIF1_TX, 261 .addr = 0xe6c50020, 262 .chcr = CHCR_TX(XMIT_SZ_8BIT), 263 .mid_rid = 0x25, 264 }, { 265 .slave_id = SHDMA_SLAVE_SCIF1_RX, 266 .addr = 0xe6c50024, 267 .chcr = CHCR_RX(XMIT_SZ_8BIT), 268 .mid_rid = 0x26, 269 }, { 270 .slave_id = SHDMA_SLAVE_SCIF2_TX, 271 .addr = 0xe6c60020, 272 .chcr = CHCR_TX(XMIT_SZ_8BIT), 273 .mid_rid = 0x29, 274 }, { 275 .slave_id = SHDMA_SLAVE_SCIF2_RX, 276 .addr = 0xe6c60024, 277 .chcr = CHCR_RX(XMIT_SZ_8BIT), 278 .mid_rid = 0x2a, 279 }, { 280 .slave_id = SHDMA_SLAVE_SCIF3_TX, 281 .addr = 0xe6c70020, 282 .chcr = CHCR_TX(XMIT_SZ_8BIT), 283 .mid_rid = 0x2d, 284 }, { 285 .slave_id = SHDMA_SLAVE_SCIF3_RX, 286 .addr = 0xe6c70024, 287 .chcr = CHCR_RX(XMIT_SZ_8BIT), 288 .mid_rid = 0x2e, 289 }, { 290 .slave_id = SHDMA_SLAVE_SCIF4_TX, 291 .addr = 0xe6c80020, 292 .chcr = CHCR_TX(XMIT_SZ_8BIT), 293 .mid_rid = 0x39, 294 }, { 295 .slave_id = SHDMA_SLAVE_SCIF4_RX, 296 .addr = 0xe6c80024, 297 .chcr = CHCR_RX(XMIT_SZ_8BIT), 298 .mid_rid = 0x3a, 299 }, { 300 .slave_id = SHDMA_SLAVE_SCIF5_TX, 301 .addr = 0xe6cb0020, 302 .chcr = CHCR_TX(XMIT_SZ_8BIT), 303 .mid_rid = 0x35, 304 }, { 305 .slave_id = SHDMA_SLAVE_SCIF5_RX, 306 .addr = 0xe6cb0024, 307 .chcr = CHCR_RX(XMIT_SZ_8BIT), 308 .mid_rid = 0x36, 309 }, { 310 .slave_id = SHDMA_SLAVE_SCIF6_TX, 311 .addr = 0xe6cc0020, 312 .chcr = CHCR_TX(XMIT_SZ_8BIT), 313 .mid_rid = 0x1d, 314 }, { 315 .slave_id = SHDMA_SLAVE_SCIF6_RX, 316 .addr = 0xe6cc0024, 317 .chcr = CHCR_RX(XMIT_SZ_8BIT), 318 .mid_rid = 0x1e, 319 }, { 320 .slave_id = SHDMA_SLAVE_SCIF7_TX, 321 .addr = 0xe6cd0020, 322 .chcr = CHCR_TX(XMIT_SZ_8BIT), 323 .mid_rid = 0x19, 324 }, { 325 .slave_id = SHDMA_SLAVE_SCIF7_RX, 326 .addr = 0xe6cd0024, 327 .chcr = CHCR_RX(XMIT_SZ_8BIT), 328 .mid_rid = 0x1a, 329 }, { 330 .slave_id = SHDMA_SLAVE_SCIF8_TX, 331 .addr = 0xe6c30040, 332 .chcr = CHCR_TX(XMIT_SZ_8BIT), 333 .mid_rid = 0x3d, 334 }, { 335 .slave_id = SHDMA_SLAVE_SCIF8_RX, 336 .addr = 0xe6c30060, 337 .chcr = CHCR_RX(XMIT_SZ_8BIT), 338 .mid_rid = 0x3e, 339 }, { 340 .slave_id = SHDMA_SLAVE_SDHI0_TX, 341 .addr = 0xee100030, 342 .chcr = CHCR_TX(XMIT_SZ_16BIT), 343 .mid_rid = 0xc1, 344 }, { 345 .slave_id = SHDMA_SLAVE_SDHI0_RX, 346 .addr = 0xee100030, 347 .chcr = CHCR_RX(XMIT_SZ_16BIT), 348 .mid_rid = 0xc2, 349 }, { 350 .slave_id = SHDMA_SLAVE_SDHI1_TX, 351 .addr = 0xee120030, 352 .chcr = CHCR_TX(XMIT_SZ_16BIT), 353 .mid_rid = 0xc9, 354 }, { 355 .slave_id = SHDMA_SLAVE_SDHI1_RX, 356 .addr = 0xee120030, 357 .chcr = CHCR_RX(XMIT_SZ_16BIT), 358 .mid_rid = 0xca, 359 }, { 360 .slave_id = SHDMA_SLAVE_SDHI2_TX, 361 .addr = 0xee140030, 362 .chcr = CHCR_TX(XMIT_SZ_16BIT), 363 .mid_rid = 0xcd, 364 }, { 365 .slave_id = SHDMA_SLAVE_SDHI2_RX, 366 .addr = 0xee140030, 367 .chcr = CHCR_RX(XMIT_SZ_16BIT), 368 .mid_rid = 0xce, 369 }, { 370 .slave_id = SHDMA_SLAVE_MMCIF_TX, 371 .addr = 0xe6bd0034, 372 .chcr = CHCR_TX(XMIT_SZ_32BIT), 373 .mid_rid = 0xd1, 374 }, { 375 .slave_id = SHDMA_SLAVE_MMCIF_RX, 376 .addr = 0xe6bd0034, 377 .chcr = CHCR_RX(XMIT_SZ_32BIT), 378 .mid_rid = 0xd2, 379 }, 380}; 381 382#define DMAE_CHANNEL(_offset) \ 383 { \ 384 .offset = _offset - 0x20, \ 385 .dmars = _offset - 0x20 + 0x40, \ 386 } 387 388static const struct sh_dmae_channel sh73a0_dmae_channels[] = { 389 DMAE_CHANNEL(0x8000), 390 DMAE_CHANNEL(0x8080), 391 DMAE_CHANNEL(0x8100), 392 DMAE_CHANNEL(0x8180), 393 DMAE_CHANNEL(0x8200), 394 DMAE_CHANNEL(0x8280), 395 DMAE_CHANNEL(0x8300), 396 DMAE_CHANNEL(0x8380), 397 DMAE_CHANNEL(0x8400), 398 DMAE_CHANNEL(0x8480), 399 DMAE_CHANNEL(0x8500), 400 DMAE_CHANNEL(0x8580), 401 DMAE_CHANNEL(0x8600), 402 DMAE_CHANNEL(0x8680), 403 DMAE_CHANNEL(0x8700), 404 DMAE_CHANNEL(0x8780), 405 DMAE_CHANNEL(0x8800), 406 DMAE_CHANNEL(0x8880), 407 DMAE_CHANNEL(0x8900), 408 DMAE_CHANNEL(0x8980), 409}; 410 411static struct sh_dmae_pdata sh73a0_dmae_platform_data = { 412 .slave = sh73a0_dmae_slaves, 413 .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves), 414 .channel = sh73a0_dmae_channels, 415 .channel_num = ARRAY_SIZE(sh73a0_dmae_channels), 416 .ts_low_shift = TS_LOW_SHIFT, 417 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, 418 .ts_high_shift = TS_HI_SHIFT, 419 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, 420 .ts_shift = dma_ts_shift, 421 .ts_shift_num = ARRAY_SIZE(dma_ts_shift), 422 .dmaor_init = DMAOR_DME, 423}; 424 425static struct resource sh73a0_dmae_resources[] = { 426 DEFINE_RES_MEM(0xfe000020, 0x89e0), 427 { 428 .name = "error_irq", 429 .start = gic_spi(129), 430 .end = gic_spi(129), 431 .flags = IORESOURCE_IRQ, 432 }, 433 { 434 /* IRQ for channels 0-19 */ 435 .start = gic_spi(109), 436 .end = gic_spi(128), 437 .flags = IORESOURCE_IRQ, 438 }, 439}; 440 441static struct platform_device dma0_device = { 442 .name = "sh-dma-engine", 443 .id = 0, 444 .resource = sh73a0_dmae_resources, 445 .num_resources = ARRAY_SIZE(sh73a0_dmae_resources), 446 .dev = { 447 .platform_data = &sh73a0_dmae_platform_data, 448 }, 449}; 450 451/* MPDMAC */ 452static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = { 453 { 454 .slave_id = SHDMA_SLAVE_FSI2A_RX, 455 .addr = 0xec230020, 456 .chcr = CHCR_RX(XMIT_SZ_32BIT), 457 .mid_rid = 0xd6, /* CHECK ME */ 458 }, { 459 .slave_id = SHDMA_SLAVE_FSI2A_TX, 460 .addr = 0xec230024, 461 .chcr = CHCR_TX(XMIT_SZ_32BIT), 462 .mid_rid = 0xd5, /* CHECK ME */ 463 }, { 464 .slave_id = SHDMA_SLAVE_FSI2C_RX, 465 .addr = 0xec230060, 466 .chcr = CHCR_RX(XMIT_SZ_32BIT), 467 .mid_rid = 0xda, /* CHECK ME */ 468 }, { 469 .slave_id = SHDMA_SLAVE_FSI2C_TX, 470 .addr = 0xec230064, 471 .chcr = CHCR_TX(XMIT_SZ_32BIT), 472 .mid_rid = 0xd9, /* CHECK ME */ 473 }, { 474 .slave_id = SHDMA_SLAVE_FSI2B_RX, 475 .addr = 0xec240020, 476 .chcr = CHCR_RX(XMIT_SZ_32BIT), 477 .mid_rid = 0x8e, /* CHECK ME */ 478 }, { 479 .slave_id = SHDMA_SLAVE_FSI2B_TX, 480 .addr = 0xec240024, 481 .chcr = CHCR_RX(XMIT_SZ_32BIT), 482 .mid_rid = 0x8d, /* CHECK ME */ 483 }, { 484 .slave_id = SHDMA_SLAVE_FSI2D_RX, 485 .addr = 0xec240060, 486 .chcr = CHCR_RX(XMIT_SZ_32BIT), 487 .mid_rid = 0x9a, /* CHECK ME */ 488 }, 489}; 490 491#define MPDMA_CHANNEL(a, b, c) \ 492{ \ 493 .offset = a, \ 494 .dmars = b, \ 495 .dmars_bit = c, \ 496 .chclr_offset = (0x220 - 0x20) + a \ 497} 498 499static const struct sh_dmae_channel sh73a0_mpdma_channels[] = { 500 MPDMA_CHANNEL(0x00, 0, 0), 501 MPDMA_CHANNEL(0x10, 0, 8), 502 MPDMA_CHANNEL(0x20, 4, 0), 503 MPDMA_CHANNEL(0x30, 4, 8), 504 MPDMA_CHANNEL(0x50, 8, 0), 505 MPDMA_CHANNEL(0x70, 8, 8), 506}; 507 508static struct sh_dmae_pdata sh73a0_mpdma_platform_data = { 509 .slave = sh73a0_mpdma_slaves, 510 .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves), 511 .channel = sh73a0_mpdma_channels, 512 .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels), 513 .ts_low_shift = TS_LOW_SHIFT, 514 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, 515 .ts_high_shift = TS_HI_SHIFT, 516 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, 517 .ts_shift = dma_ts_shift, 518 .ts_shift_num = ARRAY_SIZE(dma_ts_shift), 519 .dmaor_init = DMAOR_DME, 520 .chclr_present = 1, 521}; 522 523/* Resource order important! */ 524static struct resource sh73a0_mpdma_resources[] = { 525 /* Channel registers and DMAOR */ 526 DEFINE_RES_MEM(0xec618020, 0x270), 527 /* DMARSx */ 528 DEFINE_RES_MEM(0xec619000, 0xc), 529 { 530 .name = "error_irq", 531 .start = gic_spi(181), 532 .end = gic_spi(181), 533 .flags = IORESOURCE_IRQ, 534 }, 535 { 536 /* IRQ for channels 0-5 */ 537 .start = gic_spi(175), 538 .end = gic_spi(180), 539 .flags = IORESOURCE_IRQ, 540 }, 541}; 542 543static struct platform_device mpdma0_device = { 544 .name = "sh-dma-engine", 545 .id = 1, 546 .resource = sh73a0_mpdma_resources, 547 .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources), 548 .dev = { 549 .platform_data = &sh73a0_mpdma_platform_data, 550 }, 551}; 552 553static struct resource pmu_resources[] = { 554 [0] = { 555 .start = gic_spi(55), 556 .end = gic_spi(55), 557 .flags = IORESOURCE_IRQ, 558 }, 559 [1] = { 560 .start = gic_spi(56), 561 .end = gic_spi(56), 562 .flags = IORESOURCE_IRQ, 563 }, 564}; 565 566static struct platform_device pmu_device = { 567 .name = "armv7-pmu", 568 .id = -1, 569 .num_resources = ARRAY_SIZE(pmu_resources), 570 .resource = pmu_resources, 571}; 572 573/* an IPMMU module for ICB */ 574static struct resource ipmmu_resources[] = { 575 DEFINE_RES_MEM(0xfe951000, 0x100), 576}; 577 578static const char * const ipmmu_dev_names[] = { 579 "sh_mobile_lcdc_fb.0", 580}; 581 582static struct shmobile_ipmmu_platform_data ipmmu_platform_data = { 583 .dev_names = ipmmu_dev_names, 584 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names), 585}; 586 587static struct platform_device ipmmu_device = { 588 .name = "ipmmu", 589 .id = -1, 590 .dev = { 591 .platform_data = &ipmmu_platform_data, 592 }, 593 .resource = ipmmu_resources, 594 .num_resources = ARRAY_SIZE(ipmmu_resources), 595}; 596 597static struct renesas_intc_irqpin_config irqpin0_platform_data = { 598 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ 599 .control_parent = true, 600}; 601 602static struct resource irqpin0_resources[] = { 603 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ 604 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ 605 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ 606 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ 607 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ 608 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */ 609 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */ 610 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */ 611 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */ 612 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */ 613 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */ 614 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */ 615 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */ 616}; 617 618static struct platform_device irqpin0_device = { 619 .name = "renesas_intc_irqpin", 620 .id = 0, 621 .resource = irqpin0_resources, 622 .num_resources = ARRAY_SIZE(irqpin0_resources), 623 .dev = { 624 .platform_data = &irqpin0_platform_data, 625 }, 626}; 627 628static struct renesas_intc_irqpin_config irqpin1_platform_data = { 629 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ 630 .control_parent = true, /* Disable spurious IRQ10 */ 631}; 632 633static struct resource irqpin1_resources[] = { 634 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */ 635 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */ 636 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */ 637 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */ 638 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */ 639 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */ 640 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */ 641 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */ 642 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */ 643 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */ 644 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */ 645 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */ 646 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */ 647}; 648 649static struct platform_device irqpin1_device = { 650 .name = "renesas_intc_irqpin", 651 .id = 1, 652 .resource = irqpin1_resources, 653 .num_resources = ARRAY_SIZE(irqpin1_resources), 654 .dev = { 655 .platform_data = &irqpin1_platform_data, 656 }, 657}; 658 659static struct renesas_intc_irqpin_config irqpin2_platform_data = { 660 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ 661 .control_parent = true, 662}; 663 664static struct resource irqpin2_resources[] = { 665 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */ 666 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */ 667 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */ 668 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */ 669 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */ 670 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */ 671 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */ 672 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */ 673 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */ 674 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */ 675 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */ 676 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */ 677 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */ 678}; 679 680static struct platform_device irqpin2_device = { 681 .name = "renesas_intc_irqpin", 682 .id = 2, 683 .resource = irqpin2_resources, 684 .num_resources = ARRAY_SIZE(irqpin2_resources), 685 .dev = { 686 .platform_data = &irqpin2_platform_data, 687 }, 688}; 689 690static struct renesas_intc_irqpin_config irqpin3_platform_data = { 691 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ 692 .control_parent = true, 693}; 694 695static struct resource irqpin3_resources[] = { 696 DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */ 697 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */ 698 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */ 699 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */ 700 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */ 701 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */ 702 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */ 703 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */ 704 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */ 705 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */ 706 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */ 707 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */ 708 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */ 709}; 710 711static struct platform_device irqpin3_device = { 712 .name = "renesas_intc_irqpin", 713 .id = 3, 714 .resource = irqpin3_resources, 715 .num_resources = ARRAY_SIZE(irqpin3_resources), 716 .dev = { 717 .platform_data = &irqpin3_platform_data, 718 }, 719}; 720 721static struct platform_device *sh73a0_early_devices[] __initdata = { 722 &scif0_device, 723 &scif1_device, 724 &scif2_device, 725 &scif3_device, 726 &scif4_device, 727 &scif5_device, 728 &scif6_device, 729 &scif7_device, 730 &scif8_device, 731 &tmu0_device, 732 &ipmmu_device, 733 &cmt1_device, 734}; 735 736static struct platform_device *sh73a0_late_devices[] __initdata = { 737 &i2c0_device, 738 &i2c1_device, 739 &i2c2_device, 740 &i2c3_device, 741 &i2c4_device, 742 &dma0_device, 743 &mpdma0_device, 744 &pmu_device, 745 &irqpin0_device, 746 &irqpin1_device, 747 &irqpin2_device, 748 &irqpin3_device, 749}; 750 751#define SRCR2 IOMEM(0xe61580b0) 752 753void __init sh73a0_add_standard_devices(void) 754{ 755 /* Clear software reset bit on SY-DMAC module */ 756 __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2); 757 758 platform_add_devices(sh73a0_early_devices, 759 ARRAY_SIZE(sh73a0_early_devices)); 760 platform_add_devices(sh73a0_late_devices, 761 ARRAY_SIZE(sh73a0_late_devices)); 762} 763 764/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ 765void __init __weak sh73a0_register_twd(void) { } 766 767void __init sh73a0_earlytimer_init(void) 768{ 769 shmobile_init_delay(); 770#ifndef CONFIG_COMMON_CLK 771 sh73a0_clock_init(); 772#endif 773 shmobile_earlytimer_init(); 774 sh73a0_register_twd(); 775} 776 777void __init sh73a0_add_early_devices(void) 778{ 779 early_platform_add_devices(sh73a0_early_devices, 780 ARRAY_SIZE(sh73a0_early_devices)); 781 782 /* setup early console here as well */ 783 shmobile_setup_console(); 784} 785 786#ifdef CONFIG_USE_OF 787 788static void __init sh73a0_generic_init(void) 789{ 790#ifdef CONFIG_CACHE_L2X0 791 /* Shared attribute override enable, 64K*8way */ 792 l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff); 793#endif 794 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 795} 796 797static const char *sh73a0_boards_compat_dt[] __initdata = { 798 "renesas,sh73a0", 799 NULL, 800}; 801 802DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") 803 .smp = smp_ops(sh73a0_smp_ops), 804 .map_io = sh73a0_map_io, 805 .init_early = shmobile_init_delay, 806 .init_machine = sh73a0_generic_init, 807 .init_late = shmobile_init_late, 808 .dt_compat = sh73a0_boards_compat_dt, 809MACHINE_END 810#endif /* CONFIG_USE_OF */ 811