1/* arch/arm/mach-s3c2410/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
4 *	http://armlinux.simtec.co.uk/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 clock register definitions
11*/
12
13#ifndef __ASM_ARM_REGS_CLOCK
14#define __ASM_ARM_REGS_CLOCK
15
16#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
17
18#define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
19
20#define S3C2410_LOCKTIME    S3C2410_CLKREG(0x00)
21#define S3C2410_MPLLCON	    S3C2410_CLKREG(0x04)
22#define S3C2410_UPLLCON	    S3C2410_CLKREG(0x08)
23#define S3C2410_CLKCON	    S3C2410_CLKREG(0x0C)
24#define S3C2410_CLKSLOW	    S3C2410_CLKREG(0x10)
25#define S3C2410_CLKDIVN	    S3C2410_CLKREG(0x14)
26
27#define S3C2410_CLKCON_IDLE	     (1<<2)
28#define S3C2410_CLKCON_POWER	     (1<<3)
29#define S3C2410_CLKCON_NAND	     (1<<4)
30#define S3C2410_CLKCON_LCDC	     (1<<5)
31#define S3C2410_CLKCON_USBH	     (1<<6)
32#define S3C2410_CLKCON_USBD	     (1<<7)
33#define S3C2410_CLKCON_PWMT	     (1<<8)
34#define S3C2410_CLKCON_SDI	     (1<<9)
35#define S3C2410_CLKCON_UART0	     (1<<10)
36#define S3C2410_CLKCON_UART1	     (1<<11)
37#define S3C2410_CLKCON_UART2	     (1<<12)
38#define S3C2410_CLKCON_GPIO	     (1<<13)
39#define S3C2410_CLKCON_RTC	     (1<<14)
40#define S3C2410_CLKCON_ADC	     (1<<15)
41#define S3C2410_CLKCON_IIC	     (1<<16)
42#define S3C2410_CLKCON_IIS	     (1<<17)
43#define S3C2410_CLKCON_SPI	     (1<<18)
44
45#define S3C2410_CLKDIVN_PDIVN	     (1<<0)
46#define S3C2410_CLKDIVN_HDIVN	     (1<<1)
47
48#define S3C2410_CLKSLOW_UCLK_OFF	(1<<7)
49#define S3C2410_CLKSLOW_MPLL_OFF	(1<<5)
50#define S3C2410_CLKSLOW_SLOW		(1<<4)
51#define S3C2410_CLKSLOW_SLOWVAL(x)	(x)
52#define S3C2410_CLKSLOW_GET_SLOWVAL(x)	((x) & 7)
53
54#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
55
56/* extra registers */
57#define S3C2440_CAMDIVN	    S3C2410_CLKREG(0x18)
58
59#define S3C2440_CLKCON_CAMERA        (1<<19)
60#define S3C2440_CLKCON_AC97          (1<<20)
61
62#define S3C2440_CLKDIVN_PDIVN	     (1<<0)
63#define S3C2440_CLKDIVN_HDIVN_MASK   (3<<1)
64#define S3C2440_CLKDIVN_HDIVN_1      (0<<1)
65#define S3C2440_CLKDIVN_HDIVN_2      (1<<1)
66#define S3C2440_CLKDIVN_HDIVN_4_8    (2<<1)
67#define S3C2440_CLKDIVN_HDIVN_3_6    (3<<1)
68#define S3C2440_CLKDIVN_UCLK         (1<<3)
69
70#define S3C2440_CAMDIVN_CAMCLK_MASK  (0xf<<0)
71#define S3C2440_CAMDIVN_CAMCLK_SEL   (1<<4)
72#define S3C2440_CAMDIVN_HCLK3_HALF   (1<<8)
73#define S3C2440_CAMDIVN_HCLK4_HALF   (1<<9)
74#define S3C2440_CAMDIVN_DVSEN        (1<<12)
75
76#define S3C2442_CAMDIVN_CAMCLK_DIV3  (1<<5)
77
78#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
79
80#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
81
82#define S3C2412_OSCSET		S3C2410_CLKREG(0x18)
83#define S3C2412_CLKSRC		S3C2410_CLKREG(0x1C)
84
85#define S3C2412_PLLCON_OFF		(1<<20)
86
87#define S3C2412_CLKDIVN_PDIVN		(1<<2)
88#define S3C2412_CLKDIVN_HDIVN_MASK	(3<<0)
89#define S3C2412_CLKDIVN_ARMDIVN		(1<<3)
90#define S3C2412_CLKDIVN_DVSEN		(1<<4)
91#define S3C2412_CLKDIVN_HALFHCLK	(1<<5)
92#define S3C2412_CLKDIVN_USB48DIV	(1<<6)
93#define S3C2412_CLKDIVN_UARTDIV_MASK	(15<<8)
94#define S3C2412_CLKDIVN_UARTDIV_SHIFT	(8)
95#define S3C2412_CLKDIVN_I2SDIV_MASK	(15<<12)
96#define S3C2412_CLKDIVN_I2SDIV_SHIFT	(12)
97#define S3C2412_CLKDIVN_CAMDIV_MASK	(15<<16)
98#define S3C2412_CLKDIVN_CAMDIV_SHIFT	(16)
99
100#define S3C2412_CLKCON_WDT		(1<<28)
101#define S3C2412_CLKCON_SPI		(1<<27)
102#define S3C2412_CLKCON_IIS		(1<<26)
103#define S3C2412_CLKCON_IIC		(1<<25)
104#define S3C2412_CLKCON_ADC		(1<<24)
105#define S3C2412_CLKCON_RTC		(1<<23)
106#define S3C2412_CLKCON_GPIO		(1<<22)
107#define S3C2412_CLKCON_UART2		(1<<21)
108#define S3C2412_CLKCON_UART1		(1<<20)
109#define S3C2412_CLKCON_UART0		(1<<19)
110#define S3C2412_CLKCON_SDI		(1<<18)
111#define S3C2412_CLKCON_PWMT		(1<<17)
112#define S3C2412_CLKCON_USBD		(1<<16)
113#define S3C2412_CLKCON_CAMCLK		(1<<15)
114#define S3C2412_CLKCON_UARTCLK		(1<<14)
115/* missing 13 */
116#define S3C2412_CLKCON_USB_HOST48	(1<<12)
117#define S3C2412_CLKCON_USB_DEV48	(1<<11)
118#define S3C2412_CLKCON_HCLKdiv2		(1<<10)
119#define S3C2412_CLKCON_HCLKx2		(1<<9)
120#define S3C2412_CLKCON_SDRAM		(1<<8)
121/* missing 7 */
122#define S3C2412_CLKCON_USBH		S3C2410_CLKCON_USBH
123#define S3C2412_CLKCON_LCDC		S3C2410_CLKCON_LCDC
124#define S3C2412_CLKCON_NAND		S3C2410_CLKCON_NAND
125#define S3C2412_CLKCON_DMA3		(1<<3)
126#define S3C2412_CLKCON_DMA2		(1<<2)
127#define S3C2412_CLKCON_DMA1		(1<<1)
128#define S3C2412_CLKCON_DMA0		(1<<0)
129
130/* clock sourec controls */
131
132#define S3C2412_CLKSRC_EXTCLKDIV_MASK		(7 << 0)
133#define S3C2412_CLKSRC_EXTCLKDIV_SHIFT		(0)
134#define S3C2412_CLKSRC_MDIVCLK_EXTCLKDIV	(1<<3)
135#define S3C2412_CLKSRC_MSYSCLK_MPLL		(1<<4)
136#define S3C2412_CLKSRC_USYSCLK_UPLL		(1<<5)
137#define S3C2412_CLKSRC_UARTCLK_MPLL		(1<<8)
138#define S3C2412_CLKSRC_I2SCLK_MPLL		(1<<9)
139#define S3C2412_CLKSRC_USBCLK_HCLK		(1<<10)
140#define S3C2412_CLKSRC_CAMCLK_HCLK		(1<<11)
141#define S3C2412_CLKSRC_UREFCLK_EXTCLK	(1<<12)
142#define S3C2412_CLKSRC_EREFCLK_EXTCLK	(1<<14)
143
144#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
145
146#define S3C2416_CLKDIV2		S3C2410_CLKREG(0x28)
147
148#endif /* __ASM_ARM_REGS_CLOCK */
149