1/*
2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * XXX handle crossbar/shared link difference for L3?
13 * XXX these should be marked initdata for multi-OMAP kernels
14 */
15
16#include <linux/i2c-omap.h>
17#include <linux/platform_data/asoc-ti-mcbsp.h>
18#include <linux/platform_data/hsmmc-omap.h>
19#include <linux/platform_data/spi-omap2-mcspi.h>
20#include <linux/omap-dma.h>
21#include <plat/dmtimer.h>
22
23#include "omap_hwmod.h"
24#include "l3_2xxx.h"
25
26#include "soc.h"
27#include "omap_hwmod_common_data.h"
28#include "prm-regbits-24xx.h"
29#include "cm-regbits-24xx.h"
30#include "i2c.h"
31#include "wd_timer.h"
32
33/*
34 * OMAP2430 hardware module integration data
35 *
36 * All of the data in this section should be autogeneratable from the
37 * TI hardware database or other technical documentation.  Data that
38 * is driver-specific or driver-kernel integration-specific belongs
39 * elsewhere.
40 */
41
42/*
43 * IP blocks
44 */
45
46/* IVA2 (IVA2) */
47static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
48	{ .name = "logic", .rst_shift = 0 },
49	{ .name = "mmu", .rst_shift = 1 },
50};
51
52static struct omap_hwmod omap2430_iva_hwmod = {
53	.name		= "iva",
54	.class		= &iva_hwmod_class,
55	.clkdm_name	= "dsp_clkdm",
56	.rst_lines	= omap2430_iva_resets,
57	.rst_lines_cnt	= ARRAY_SIZE(omap2430_iva_resets),
58	.main_clk	= "dsp_fck",
59};
60
61/* I2C common */
62static struct omap_hwmod_class_sysconfig i2c_sysc = {
63	.rev_offs	= 0x00,
64	.sysc_offs	= 0x20,
65	.syss_offs	= 0x10,
66	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
67			   SYSS_HAS_RESET_STATUS),
68	.sysc_fields	= &omap_hwmod_sysc_type1,
69};
70
71static struct omap_hwmod_class i2c_class = {
72	.name		= "i2c",
73	.sysc		= &i2c_sysc,
74	.rev		= OMAP_I2C_IP_VERSION_1,
75	.reset		= &omap_i2c_reset,
76};
77
78static struct omap_i2c_dev_attr i2c_dev_attr = {
79	.fifo_depth	= 8, /* bytes */
80	.flags		= OMAP_I2C_FLAG_BUS_SHIFT_2 |
81			  OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
82};
83
84/* I2C1 */
85static struct omap_hwmod omap2430_i2c1_hwmod = {
86	.name		= "i2c1",
87	.flags		= HWMOD_16BIT_REG,
88	.main_clk	= "i2chs1_fck",
89	.prcm		= {
90		.omap2 = {
91			/*
92			 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
93			 * I2CHS IP's do not follow the usual pattern.
94			 * prcm_reg_id alone cannot be used to program
95			 * the iclk and fclk. Needs to be handled using
96			 * additional flags when clk handling is moved
97			 * to hwmod framework.
98			 */
99			.module_offs = CORE_MOD,
100			.prcm_reg_id = 1,
101			.module_bit = OMAP2430_EN_I2CHS1_SHIFT,
102			.idlest_reg_id = 1,
103			.idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
104		},
105	},
106	.class		= &i2c_class,
107	.dev_attr	= &i2c_dev_attr,
108};
109
110/* I2C2 */
111static struct omap_hwmod omap2430_i2c2_hwmod = {
112	.name		= "i2c2",
113	.flags		= HWMOD_16BIT_REG,
114	.main_clk	= "i2chs2_fck",
115	.prcm		= {
116		.omap2 = {
117			.module_offs = CORE_MOD,
118			.prcm_reg_id = 1,
119			.module_bit = OMAP2430_EN_I2CHS2_SHIFT,
120			.idlest_reg_id = 1,
121			.idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
122		},
123	},
124	.class		= &i2c_class,
125	.dev_attr	= &i2c_dev_attr,
126};
127
128/* gpio5 */
129static struct omap_hwmod omap2430_gpio5_hwmod = {
130	.name		= "gpio5",
131	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
132	.main_clk	= "gpio5_fck",
133	.prcm		= {
134		.omap2 = {
135			.prcm_reg_id = 2,
136			.module_bit = OMAP2430_EN_GPIO5_SHIFT,
137			.module_offs = CORE_MOD,
138			.idlest_reg_id = 2,
139			.idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
140		},
141	},
142	.class		= &omap2xxx_gpio_hwmod_class,
143	.dev_attr	= &omap2xxx_gpio_dev_attr,
144};
145
146/* dma attributes */
147static struct omap_dma_dev_attr dma_dev_attr = {
148	.dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
149				IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
150	.lch_count = 32,
151};
152
153static struct omap_hwmod omap2430_dma_system_hwmod = {
154	.name		= "dma",
155	.class		= &omap2xxx_dma_hwmod_class,
156	.mpu_irqs	= omap2_dma_system_irqs,
157	.main_clk	= "core_l3_ck",
158	.dev_attr	= &dma_dev_attr,
159	.flags		= HWMOD_NO_IDLEST,
160};
161
162/* mailbox */
163static struct omap_hwmod omap2430_mailbox_hwmod = {
164	.name		= "mailbox",
165	.class		= &omap2xxx_mailbox_hwmod_class,
166	.main_clk	= "mailboxes_ick",
167	.prcm		= {
168		.omap2 = {
169			.prcm_reg_id = 1,
170			.module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
171			.module_offs = CORE_MOD,
172			.idlest_reg_id = 1,
173			.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
174		},
175	},
176};
177
178/* mcspi3 */
179static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
180	.num_chipselect = 2,
181};
182
183static struct omap_hwmod omap2430_mcspi3_hwmod = {
184	.name		= "mcspi3",
185	.main_clk	= "mcspi3_fck",
186	.prcm		= {
187		.omap2 = {
188			.module_offs = CORE_MOD,
189			.prcm_reg_id = 2,
190			.module_bit = OMAP2430_EN_MCSPI3_SHIFT,
191			.idlest_reg_id = 2,
192			.idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
193		},
194	},
195	.class		= &omap2xxx_mcspi_class,
196	.dev_attr	= &omap_mcspi3_dev_attr,
197};
198
199/* usbhsotg */
200static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
201	.rev_offs	= 0x0400,
202	.sysc_offs	= 0x0404,
203	.syss_offs	= 0x0408,
204	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
205			  SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
206			  SYSC_HAS_AUTOIDLE),
207	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
208			  MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
209	.sysc_fields	= &omap_hwmod_sysc_type1,
210};
211
212static struct omap_hwmod_class usbotg_class = {
213	.name = "usbotg",
214	.sysc = &omap2430_usbhsotg_sysc,
215};
216
217/* usb_otg_hs */
218static struct omap_hwmod omap2430_usbhsotg_hwmod = {
219	.name		= "usb_otg_hs",
220	.main_clk	= "usbhs_ick",
221	.prcm		= {
222		.omap2 = {
223			.prcm_reg_id = 1,
224			.module_bit = OMAP2430_EN_USBHS_MASK,
225			.module_offs = CORE_MOD,
226			.idlest_reg_id = 1,
227			.idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
228		},
229	},
230	.class		= &usbotg_class,
231	/*
232	 * Erratum ID: i479  idle_req / idle_ack mechanism potentially
233	 * broken when autoidle is enabled
234	 * workaround is to disable the autoidle bit at module level.
235	 */
236	.flags		= HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
237				| HWMOD_SWSUP_MSTANDBY,
238};
239
240/*
241 * 'mcbsp' class
242 * multi channel buffered serial port controller
243 */
244
245static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
246	.rev_offs	= 0x007C,
247	.sysc_offs	= 0x008C,
248	.sysc_flags	= (SYSC_HAS_SOFTRESET),
249	.sysc_fields    = &omap_hwmod_sysc_type1,
250};
251
252static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
253	.name = "mcbsp",
254	.sysc = &omap2430_mcbsp_sysc,
255	.rev  = MCBSP_CONFIG_TYPE2,
256};
257
258static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
259	{ .role = "pad_fck", .clk = "mcbsp_clks" },
260	{ .role = "prcm_fck", .clk = "func_96m_ck" },
261};
262
263/* mcbsp1 */
264static struct omap_hwmod omap2430_mcbsp1_hwmod = {
265	.name		= "mcbsp1",
266	.class		= &omap2430_mcbsp_hwmod_class,
267	.main_clk	= "mcbsp1_fck",
268	.prcm		= {
269		.omap2 = {
270			.prcm_reg_id = 1,
271			.module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
272			.module_offs = CORE_MOD,
273			.idlest_reg_id = 1,
274			.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
275		},
276	},
277	.opt_clks	= mcbsp_opt_clks,
278	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
279};
280
281/* mcbsp2 */
282static struct omap_hwmod omap2430_mcbsp2_hwmod = {
283	.name		= "mcbsp2",
284	.class		= &omap2430_mcbsp_hwmod_class,
285	.main_clk	= "mcbsp2_fck",
286	.prcm		= {
287		.omap2 = {
288			.prcm_reg_id = 1,
289			.module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
290			.module_offs = CORE_MOD,
291			.idlest_reg_id = 1,
292			.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
293		},
294	},
295	.opt_clks	= mcbsp_opt_clks,
296	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
297};
298
299/* mcbsp3 */
300static struct omap_hwmod omap2430_mcbsp3_hwmod = {
301	.name		= "mcbsp3",
302	.class		= &omap2430_mcbsp_hwmod_class,
303	.main_clk	= "mcbsp3_fck",
304	.prcm		= {
305		.omap2 = {
306			.prcm_reg_id = 1,
307			.module_bit = OMAP2430_EN_MCBSP3_SHIFT,
308			.module_offs = CORE_MOD,
309			.idlest_reg_id = 2,
310			.idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
311		},
312	},
313	.opt_clks	= mcbsp_opt_clks,
314	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
315};
316
317/* mcbsp4 */
318static struct omap_hwmod omap2430_mcbsp4_hwmod = {
319	.name		= "mcbsp4",
320	.class		= &omap2430_mcbsp_hwmod_class,
321	.main_clk	= "mcbsp4_fck",
322	.prcm		= {
323		.omap2 = {
324			.prcm_reg_id = 1,
325			.module_bit = OMAP2430_EN_MCBSP4_SHIFT,
326			.module_offs = CORE_MOD,
327			.idlest_reg_id = 2,
328			.idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
329		},
330	},
331	.opt_clks	= mcbsp_opt_clks,
332	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
333};
334
335/* mcbsp5 */
336static struct omap_hwmod omap2430_mcbsp5_hwmod = {
337	.name		= "mcbsp5",
338	.class		= &omap2430_mcbsp_hwmod_class,
339	.main_clk	= "mcbsp5_fck",
340	.prcm		= {
341		.omap2 = {
342			.prcm_reg_id = 1,
343			.module_bit = OMAP2430_EN_MCBSP5_SHIFT,
344			.module_offs = CORE_MOD,
345			.idlest_reg_id = 2,
346			.idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
347		},
348	},
349	.opt_clks	= mcbsp_opt_clks,
350	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
351};
352
353/* MMC/SD/SDIO common */
354static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
355	.rev_offs	= 0x1fc,
356	.sysc_offs	= 0x10,
357	.syss_offs	= 0x14,
358	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
359			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
360			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
361	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
362	.sysc_fields    = &omap_hwmod_sysc_type1,
363};
364
365static struct omap_hwmod_class omap2430_mmc_class = {
366	.name = "mmc",
367	.sysc = &omap2430_mmc_sysc,
368};
369
370/* MMC/SD/SDIO1 */
371static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
372	{ .role = "dbck", .clk = "mmchsdb1_fck" },
373};
374
375static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
376	.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
377};
378
379static struct omap_hwmod omap2430_mmc1_hwmod = {
380	.name		= "mmc1",
381	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
382	.opt_clks	= omap2430_mmc1_opt_clks,
383	.opt_clks_cnt	= ARRAY_SIZE(omap2430_mmc1_opt_clks),
384	.main_clk	= "mmchs1_fck",
385	.prcm		= {
386		.omap2 = {
387			.module_offs = CORE_MOD,
388			.prcm_reg_id = 2,
389			.module_bit  = OMAP2430_EN_MMCHS1_SHIFT,
390			.idlest_reg_id = 2,
391			.idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
392		},
393	},
394	.dev_attr	= &mmc1_dev_attr,
395	.class		= &omap2430_mmc_class,
396};
397
398/* MMC/SD/SDIO2 */
399static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
400	{ .role = "dbck", .clk = "mmchsdb2_fck" },
401};
402
403static struct omap_hwmod omap2430_mmc2_hwmod = {
404	.name		= "mmc2",
405	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
406	.opt_clks	= omap2430_mmc2_opt_clks,
407	.opt_clks_cnt	= ARRAY_SIZE(omap2430_mmc2_opt_clks),
408	.main_clk	= "mmchs2_fck",
409	.prcm		= {
410		.omap2 = {
411			.module_offs = CORE_MOD,
412			.prcm_reg_id = 2,
413			.module_bit  = OMAP2430_EN_MMCHS2_SHIFT,
414			.idlest_reg_id = 2,
415			.idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
416		},
417	},
418	.class		= &omap2430_mmc_class,
419};
420
421/* HDQ1W/1-wire */
422static struct omap_hwmod omap2430_hdq1w_hwmod = {
423	.name		= "hdq1w",
424	.main_clk	= "hdq_fck",
425	.prcm		= {
426		.omap2 = {
427			.module_offs = CORE_MOD,
428			.prcm_reg_id = 1,
429			.module_bit = OMAP24XX_EN_HDQ_SHIFT,
430			.idlest_reg_id = 1,
431			.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
432		},
433	},
434	.class		= &omap2_hdq1w_class,
435};
436
437/*
438 * interfaces
439 */
440
441/* L3 -> L4_CORE interface */
442/* l3_core -> usbhsotg  interface */
443static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
444	.master		= &omap2430_usbhsotg_hwmod,
445	.slave		= &omap2xxx_l3_main_hwmod,
446	.clk		= "core_l3_ck",
447	.user		= OCP_USER_MPU,
448};
449
450/* L4 CORE -> I2C1 interface */
451static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
452	.master		= &omap2xxx_l4_core_hwmod,
453	.slave		= &omap2430_i2c1_hwmod,
454	.clk		= "i2c1_ick",
455	.user		= OCP_USER_MPU | OCP_USER_SDMA,
456};
457
458/* L4 CORE -> I2C2 interface */
459static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
460	.master		= &omap2xxx_l4_core_hwmod,
461	.slave		= &omap2430_i2c2_hwmod,
462	.clk		= "i2c2_ick",
463	.user		= OCP_USER_MPU | OCP_USER_SDMA,
464};
465
466/*  l4_core ->usbhsotg  interface */
467static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
468	.master		= &omap2xxx_l4_core_hwmod,
469	.slave		= &omap2430_usbhsotg_hwmod,
470	.clk		= "usb_l4_ick",
471	.user		= OCP_USER_MPU,
472};
473
474/* L4 CORE -> MMC1 interface */
475static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
476	.master		= &omap2xxx_l4_core_hwmod,
477	.slave		= &omap2430_mmc1_hwmod,
478	.clk		= "mmchs1_ick",
479	.user		= OCP_USER_MPU | OCP_USER_SDMA,
480};
481
482/* L4 CORE -> MMC2 interface */
483static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
484	.master		= &omap2xxx_l4_core_hwmod,
485	.slave		= &omap2430_mmc2_hwmod,
486	.clk		= "mmchs2_ick",
487	.user		= OCP_USER_MPU | OCP_USER_SDMA,
488};
489
490/* l4 core -> mcspi3 interface */
491static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
492	.master		= &omap2xxx_l4_core_hwmod,
493	.slave		= &omap2430_mcspi3_hwmod,
494	.clk		= "mcspi3_ick",
495	.user		= OCP_USER_MPU | OCP_USER_SDMA,
496};
497
498/* IVA2 <- L3 interface */
499static struct omap_hwmod_ocp_if omap2430_l3__iva = {
500	.master		= &omap2xxx_l3_main_hwmod,
501	.slave		= &omap2430_iva_hwmod,
502	.clk		= "core_l3_ck",
503	.user		= OCP_USER_MPU | OCP_USER_SDMA,
504};
505
506/* l4_wkup -> timer1 */
507static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
508	.master		= &omap2xxx_l4_wkup_hwmod,
509	.slave		= &omap2xxx_timer1_hwmod,
510	.clk		= "gpt1_ick",
511	.user		= OCP_USER_MPU | OCP_USER_SDMA,
512};
513
514/* l4_wkup -> wd_timer2 */
515static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
516	.master		= &omap2xxx_l4_wkup_hwmod,
517	.slave		= &omap2xxx_wd_timer2_hwmod,
518	.clk		= "mpu_wdt_ick",
519	.user		= OCP_USER_MPU | OCP_USER_SDMA,
520};
521
522/* l4_wkup -> gpio1 */
523static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
524	.master		= &omap2xxx_l4_wkup_hwmod,
525	.slave		= &omap2xxx_gpio1_hwmod,
526	.clk		= "gpios_ick",
527	.user		= OCP_USER_MPU | OCP_USER_SDMA,
528};
529
530/* l4_wkup -> gpio2 */
531static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
532	.master		= &omap2xxx_l4_wkup_hwmod,
533	.slave		= &omap2xxx_gpio2_hwmod,
534	.clk		= "gpios_ick",
535	.user		= OCP_USER_MPU | OCP_USER_SDMA,
536};
537
538/* l4_wkup -> gpio3 */
539static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
540	.master		= &omap2xxx_l4_wkup_hwmod,
541	.slave		= &omap2xxx_gpio3_hwmod,
542	.clk		= "gpios_ick",
543	.user		= OCP_USER_MPU | OCP_USER_SDMA,
544};
545
546/* l4_wkup -> gpio4 */
547static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
548	.master		= &omap2xxx_l4_wkup_hwmod,
549	.slave		= &omap2xxx_gpio4_hwmod,
550	.clk		= "gpios_ick",
551	.user		= OCP_USER_MPU | OCP_USER_SDMA,
552};
553
554/* l4_core -> gpio5 */
555static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
556	.master		= &omap2xxx_l4_core_hwmod,
557	.slave		= &omap2430_gpio5_hwmod,
558	.clk		= "gpio5_ick",
559	.user		= OCP_USER_MPU | OCP_USER_SDMA,
560};
561
562/* dma_system -> L3 */
563static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
564	.master		= &omap2430_dma_system_hwmod,
565	.slave		= &omap2xxx_l3_main_hwmod,
566	.clk		= "core_l3_ck",
567	.user		= OCP_USER_MPU | OCP_USER_SDMA,
568};
569
570/* l4_core -> dma_system */
571static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
572	.master		= &omap2xxx_l4_core_hwmod,
573	.slave		= &omap2430_dma_system_hwmod,
574	.clk		= "sdma_ick",
575	.addr		= omap2_dma_system_addrs,
576	.user		= OCP_USER_MPU | OCP_USER_SDMA,
577};
578
579/* l4_core -> mailbox */
580static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
581	.master		= &omap2xxx_l4_core_hwmod,
582	.slave		= &omap2430_mailbox_hwmod,
583	.user		= OCP_USER_MPU | OCP_USER_SDMA,
584};
585
586/* l4_core -> mcbsp1 */
587static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
588	.master		= &omap2xxx_l4_core_hwmod,
589	.slave		= &omap2430_mcbsp1_hwmod,
590	.clk		= "mcbsp1_ick",
591	.user		= OCP_USER_MPU | OCP_USER_SDMA,
592};
593
594/* l4_core -> mcbsp2 */
595static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
596	.master		= &omap2xxx_l4_core_hwmod,
597	.slave		= &omap2430_mcbsp2_hwmod,
598	.clk		= "mcbsp2_ick",
599	.user		= OCP_USER_MPU | OCP_USER_SDMA,
600};
601
602/* l4_core -> mcbsp3 */
603static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
604	.master		= &omap2xxx_l4_core_hwmod,
605	.slave		= &omap2430_mcbsp3_hwmod,
606	.clk		= "mcbsp3_ick",
607	.user		= OCP_USER_MPU | OCP_USER_SDMA,
608};
609
610/* l4_core -> mcbsp4 */
611static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
612	.master		= &omap2xxx_l4_core_hwmod,
613	.slave		= &omap2430_mcbsp4_hwmod,
614	.clk		= "mcbsp4_ick",
615	.user		= OCP_USER_MPU | OCP_USER_SDMA,
616};
617
618/* l4_core -> mcbsp5 */
619static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
620	.master		= &omap2xxx_l4_core_hwmod,
621	.slave		= &omap2430_mcbsp5_hwmod,
622	.clk		= "mcbsp5_ick",
623	.user		= OCP_USER_MPU | OCP_USER_SDMA,
624};
625
626/* l4_core -> hdq1w */
627static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
628	.master		= &omap2xxx_l4_core_hwmod,
629	.slave		= &omap2430_hdq1w_hwmod,
630	.clk		= "hdq_ick",
631	.user		= OCP_USER_MPU | OCP_USER_SDMA,
632	.flags		= OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
633};
634
635/* l4_wkup -> 32ksync_counter */
636static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
637	.master		= &omap2xxx_l4_wkup_hwmod,
638	.slave		= &omap2xxx_counter_32k_hwmod,
639	.clk		= "sync_32k_ick",
640	.user		= OCP_USER_MPU | OCP_USER_SDMA,
641};
642
643static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
644	.master		= &omap2xxx_l3_main_hwmod,
645	.slave		= &omap2xxx_gpmc_hwmod,
646	.clk		= "core_l3_ck",
647	.user		= OCP_USER_MPU | OCP_USER_SDMA,
648};
649
650static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
651	&omap2xxx_l3_main__l4_core,
652	&omap2xxx_mpu__l3_main,
653	&omap2xxx_dss__l3,
654	&omap2430_usbhsotg__l3,
655	&omap2430_l4_core__i2c1,
656	&omap2430_l4_core__i2c2,
657	&omap2xxx_l4_core__l4_wkup,
658	&omap2_l4_core__uart1,
659	&omap2_l4_core__uart2,
660	&omap2_l4_core__uart3,
661	&omap2430_l4_core__usbhsotg,
662	&omap2430_l4_core__mmc1,
663	&omap2430_l4_core__mmc2,
664	&omap2xxx_l4_core__mcspi1,
665	&omap2xxx_l4_core__mcspi2,
666	&omap2430_l4_core__mcspi3,
667	&omap2430_l3__iva,
668	&omap2430_l4_wkup__timer1,
669	&omap2xxx_l4_core__timer2,
670	&omap2xxx_l4_core__timer3,
671	&omap2xxx_l4_core__timer4,
672	&omap2xxx_l4_core__timer5,
673	&omap2xxx_l4_core__timer6,
674	&omap2xxx_l4_core__timer7,
675	&omap2xxx_l4_core__timer8,
676	&omap2xxx_l4_core__timer9,
677	&omap2xxx_l4_core__timer10,
678	&omap2xxx_l4_core__timer11,
679	&omap2xxx_l4_core__timer12,
680	&omap2430_l4_wkup__wd_timer2,
681	&omap2xxx_l4_core__dss,
682	&omap2xxx_l4_core__dss_dispc,
683	&omap2xxx_l4_core__dss_rfbi,
684	&omap2xxx_l4_core__dss_venc,
685	&omap2430_l4_wkup__gpio1,
686	&omap2430_l4_wkup__gpio2,
687	&omap2430_l4_wkup__gpio3,
688	&omap2430_l4_wkup__gpio4,
689	&omap2430_l4_core__gpio5,
690	&omap2430_dma_system__l3,
691	&omap2430_l4_core__dma_system,
692	&omap2430_l4_core__mailbox,
693	&omap2430_l4_core__mcbsp1,
694	&omap2430_l4_core__mcbsp2,
695	&omap2430_l4_core__mcbsp3,
696	&omap2430_l4_core__mcbsp4,
697	&omap2430_l4_core__mcbsp5,
698	&omap2430_l4_core__hdq1w,
699	&omap2xxx_l4_core__rng,
700	&omap2xxx_l4_core__sham,
701	&omap2xxx_l4_core__aes,
702	&omap2430_l4_wkup__counter_32k,
703	&omap2430_l3__gpmc,
704	NULL,
705};
706
707int __init omap2430_hwmod_init(void)
708{
709	omap_hwmod_init();
710	return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
711}
712