1/*
2 * IP block integration code for the HDQ1W/1-wire IP block
3 *
4 * Copyright (C) 2012 Texas Instruments, Inc.
5 * Paul Walmsley
6 *
7 * Based on the I2C reset code in arch/arm/mach-omap2/i2c.c by
8 *     Avinash.H.M <avinashhm@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * 02110-1301 USA
23 */
24
25#include <linux/kernel.h>
26#include <linux/init.h>
27#include <linux/err.h>
28#include <linux/platform_device.h>
29
30#include "soc.h"
31#include "omap_hwmod.h"
32#include "omap_device.h"
33#include "hdq1w.h"
34
35#include "prm.h"
36#include "common.h"
37
38/**
39 * omap_hdq1w_reset - reset the OMAP HDQ1W module
40 * @oh: struct omap_hwmod *
41 *
42 * OCP soft reset the HDQ1W IP block.  Section 20.6.1.4 "HDQ1W/1-Wire
43 * Software Reset" of the OMAP34xx Technical Reference Manual Revision
44 * ZR (SWPU223R) does not include the rather important fact that, for
45 * the reset to succeed, the HDQ1W module's internal clock gate must be
46 * programmed to allow the clock to propagate to the rest of the
47 * module.  In this sense, it's rather similar to the I2C custom reset
48 * function.  Returns 0.
49 */
50int omap_hdq1w_reset(struct omap_hwmod *oh)
51{
52	u32 v;
53	int c = 0;
54
55	/* Write to the SOFTRESET bit */
56	omap_hwmod_softreset(oh);
57
58	/* Enable the module's internal clocks */
59	v = omap_hwmod_read(oh, HDQ_CTRL_STATUS_OFFSET);
60	v |= 1 << HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT;
61	omap_hwmod_write(v, oh, HDQ_CTRL_STATUS_OFFSET);
62
63	/* Poll on RESETDONE bit */
64	omap_test_timeout((omap_hwmod_read(oh,
65					   oh->class->sysc->syss_offs)
66			   & SYSS_RESETDONE_MASK),
67			  MAX_MODULE_SOFTRESET_WAIT, c);
68
69	if (c == MAX_MODULE_SOFTRESET_WAIT)
70		pr_warn("%s: %s: softreset failed (waited %d usec)\n",
71			__func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
72	else
73		pr_debug("%s: %s: softreset in %d usec\n", __func__,
74			 oh->name, c);
75
76	return 0;
77}
78
79#ifndef CONFIG_OF
80static int __init omap_init_hdq(void)
81{
82	int id = -1;
83	struct platform_device *pdev;
84	struct omap_hwmod *oh;
85	char *oh_name = "hdq1w";
86	char *devname = "omap_hdq";
87
88	oh = omap_hwmod_lookup(oh_name);
89	if (!oh)
90		return 0;
91
92	pdev = omap_device_build(devname, id, oh, NULL, 0);
93	WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
94	     devname, oh->name);
95
96	return 0;
97}
98omap_arch_initcall(omap_init_hdq);
99#endif
100