1/* 2 * linux/arch/arm/mach-omap1/ams-delta-fiq-handler.S 3 * 4 * Based on linux/arch/arm/lib/floppydma.S 5 * Renamed and modified to work with 2.6 kernel by Matt Callow 6 * Copyright (C) 1995, 1996 Russell King 7 * Copyright (C) 2004 Pete Trapps 8 * Copyright (C) 2006 Matt Callow 9 * Copyright (C) 2010 Janusz Krzysztofik 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License version 2 13 * as published by the Free Software Foundation. 14 */ 15 16#include <linux/linkage.h> 17#include <asm/assembler.h> 18 19#include <mach/board-ams-delta.h> 20 21#include <mach/irqs.h> 22#include <mach/ams-delta-fiq.h> 23 24#include "iomap.h" 25 26/* 27 * GPIO related definitions, copied from arch/arm/plat-omap/gpio.c. 28 * Unfortunately, those were not placed in a separate header file. 29 */ 30#define OMAP1510_GPIO_BASE 0xFFFCE000 31#define OMAP1510_GPIO_DATA_INPUT 0x00 32#define OMAP1510_GPIO_DATA_OUTPUT 0x04 33#define OMAP1510_GPIO_DIR_CONTROL 0x08 34#define OMAP1510_GPIO_INT_CONTROL 0x0c 35#define OMAP1510_GPIO_INT_MASK 0x10 36#define OMAP1510_GPIO_INT_STATUS 0x14 37#define OMAP1510_GPIO_PIN_CONTROL 0x18 38 39/* GPIO register bitmasks */ 40#define KEYBRD_DATA_MASK (0x1 << AMS_DELTA_GPIO_PIN_KEYBRD_DATA) 41#define KEYBRD_CLK_MASK (0x1 << AMS_DELTA_GPIO_PIN_KEYBRD_CLK) 42#define MODEM_IRQ_MASK (0x1 << AMS_DELTA_GPIO_PIN_MODEM_IRQ) 43#define HOOK_SWITCH_MASK (0x1 << AMS_DELTA_GPIO_PIN_HOOK_SWITCH) 44#define OTHERS_MASK (MODEM_IRQ_MASK | HOOK_SWITCH_MASK) 45 46/* IRQ handler register bitmasks */ 47#define DEFERRED_FIQ_MASK (0x1 << (INT_DEFERRED_FIQ % IH2_BASE)) 48#define GPIO_BANK1_MASK (0x1 << INT_GPIO_BANK1) 49 50/* Driver buffer byte offsets */ 51#define BUF_MASK (FIQ_MASK * 4) 52#define BUF_STATE (FIQ_STATE * 4) 53#define BUF_KEYS_CNT (FIQ_KEYS_CNT * 4) 54#define BUF_TAIL_OFFSET (FIQ_TAIL_OFFSET * 4) 55#define BUF_HEAD_OFFSET (FIQ_HEAD_OFFSET * 4) 56#define BUF_BUF_LEN (FIQ_BUF_LEN * 4) 57#define BUF_KEY (FIQ_KEY * 4) 58#define BUF_MISSED_KEYS (FIQ_MISSED_KEYS * 4) 59#define BUF_BUFFER_START (FIQ_BUFFER_START * 4) 60#define BUF_GPIO_INT_MASK (FIQ_GPIO_INT_MASK * 4) 61#define BUF_KEYS_HICNT (FIQ_KEYS_HICNT * 4) 62#define BUF_IRQ_PEND (FIQ_IRQ_PEND * 4) 63#define BUF_SIR_CODE_L1 (FIQ_SIR_CODE_L1 * 4) 64#define BUF_SIR_CODE_L2 (IRQ_SIR_CODE_L2 * 4) 65#define BUF_CNT_INT_00 (FIQ_CNT_INT_00 * 4) 66#define BUF_CNT_INT_KEY (FIQ_CNT_INT_KEY * 4) 67#define BUF_CNT_INT_MDM (FIQ_CNT_INT_MDM * 4) 68#define BUF_CNT_INT_03 (FIQ_CNT_INT_03 * 4) 69#define BUF_CNT_INT_HSW (FIQ_CNT_INT_HSW * 4) 70#define BUF_CNT_INT_05 (FIQ_CNT_INT_05 * 4) 71#define BUF_CNT_INT_06 (FIQ_CNT_INT_06 * 4) 72#define BUF_CNT_INT_07 (FIQ_CNT_INT_07 * 4) 73#define BUF_CNT_INT_08 (FIQ_CNT_INT_08 * 4) 74#define BUF_CNT_INT_09 (FIQ_CNT_INT_09 * 4) 75#define BUF_CNT_INT_10 (FIQ_CNT_INT_10 * 4) 76#define BUF_CNT_INT_11 (FIQ_CNT_INT_11 * 4) 77#define BUF_CNT_INT_12 (FIQ_CNT_INT_12 * 4) 78#define BUF_CNT_INT_13 (FIQ_CNT_INT_13 * 4) 79#define BUF_CNT_INT_14 (FIQ_CNT_INT_14 * 4) 80#define BUF_CNT_INT_15 (FIQ_CNT_INT_15 * 4) 81#define BUF_CIRC_BUFF (FIQ_CIRC_BUFF * 4) 82 83 84/* 85 * Register usage 86 * r8 - temporary 87 * r9 - the driver buffer 88 * r10 - temporary 89 * r11 - interrupts mask 90 * r12 - base pointers 91 * r13 - interrupts status 92 */ 93 94 .text 95 96 .global qwerty_fiqin_end 97 98ENTRY(qwerty_fiqin_start) 99 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 100 @ FIQ intrrupt handler 101 ldr r12, omap_ih1_base @ set pointer to level1 handler 102 103 ldr r11, [r12, #IRQ_MIR_REG_OFFSET] @ fetch interrupts mask 104 105 ldr r13, [r12, #IRQ_ITR_REG_OFFSET] @ fetch interrupts status 106 bics r13, r13, r11 @ clear masked - any left? 107 beq exit @ none - spurious FIQ? exit 108 109 ldr r10, [r12, #IRQ_SIR_FIQ_REG_OFFSET] @ get requested interrupt number 110 111 mov r8, #2 @ reset FIQ agreement 112 str r8, [r12, #IRQ_CONTROL_REG_OFFSET] 113 114 cmp r10, #INT_GPIO_BANK1 @ is it GPIO bank interrupt? 115 beq gpio @ yes - process it 116 117 mov r8, #1 118 orr r8, r11, r8, lsl r10 @ mask spurious interrupt 119 str r8, [r12, #IRQ_MIR_REG_OFFSET] 120exit: 121 subs pc, lr, #4 @ return from FIQ 122 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 123 124 125 @@@@@@@@@@@@@@@@@@@@@@@@@@@ 126gpio: @ GPIO bank interrupt handler 127 ldr r12, omap1510_gpio_base @ set base pointer to GPIO bank 128 129 ldr r11, [r12, #OMAP1510_GPIO_INT_MASK] @ fetch GPIO interrupts mask 130restart: 131 ldr r13, [r12, #OMAP1510_GPIO_INT_STATUS] @ fetch status bits 132 bics r13, r13, r11 @ clear masked - any left? 133 beq exit @ no - spurious interrupt? exit 134 135 orr r11, r11, r13 @ mask all requested interrupts 136 str r11, [r12, #OMAP1510_GPIO_INT_MASK] 137 138 ands r10, r13, #KEYBRD_CLK_MASK @ extract keyboard status - set? 139 beq hksw @ no - try next source 140 141 142 @@@@@@@@@@@@@@@@@@@@@@ 143 @ Keyboard clock FIQ mode interrupt handler 144 @ r10 now contains KEYBRD_CLK_MASK, use it 145 str r10, [r12, #OMAP1510_GPIO_INT_STATUS] @ ack the interrupt 146 bic r11, r11, r10 @ unmask it 147 str r11, [r12, #OMAP1510_GPIO_INT_MASK] 148 149 @ Process keyboard data 150 ldr r8, [r12, #OMAP1510_GPIO_DATA_INPUT] @ fetch GPIO input 151 152 ldr r10, [r9, #BUF_STATE] @ fetch kbd interface state 153 cmp r10, #0 @ are we expecting start bit? 154 bne data @ no - go to data processing 155 156 ands r8, r8, #KEYBRD_DATA_MASK @ check start bit - detected? 157 beq hksw @ no - try next source 158 159 @ r8 contains KEYBRD_DATA_MASK, use it 160 str r8, [r9, #BUF_STATE] @ enter data processing state 161 @ r10 already contains 0, reuse it 162 str r10, [r9, #BUF_KEY] @ clear keycode 163 mov r10, #2 @ reset input bit mask 164 str r10, [r9, #BUF_MASK] 165 166 @ Mask other GPIO line interrupts till key done 167 str r11, [r9, #BUF_GPIO_INT_MASK] @ save mask for later restore 168 mvn r11, #KEYBRD_CLK_MASK @ prepare all except kbd mask 169 str r11, [r12, #OMAP1510_GPIO_INT_MASK] @ store into the mask register 170 171 b restart @ restart 172 173data: ldr r10, [r9, #BUF_MASK] @ fetch current input bit mask 174 175 @ r8 still contains GPIO input bits 176 ands r8, r8, #KEYBRD_DATA_MASK @ is keyboard data line low? 177 ldreq r8, [r9, #BUF_KEY] @ yes - fetch collected so far, 178 orreq r8, r8, r10 @ set 1 at current mask position 179 streq r8, [r9, #BUF_KEY] @ and save back 180 181 mov r10, r10, lsl #1 @ shift mask left 182 bics r10, r10, #0x800 @ have we got all the bits? 183 strne r10, [r9, #BUF_MASK] @ not yet - store the mask 184 bne restart @ and restart 185 186 @ r10 already contains 0, reuse it 187 str r10, [r9, #BUF_STATE] @ reset state to start 188 189 @ Key done - restore interrupt mask 190 ldr r10, [r9, #BUF_GPIO_INT_MASK] @ fetch saved mask 191 and r11, r11, r10 @ unmask all saved as unmasked 192 str r11, [r12, #OMAP1510_GPIO_INT_MASK] @ restore into the mask register 193 194 @ Try appending the keycode to the circular buffer 195 ldr r10, [r9, #BUF_KEYS_CNT] @ get saved keystrokes count 196 ldr r8, [r9, #BUF_BUF_LEN] @ get buffer size 197 cmp r10, r8 @ is buffer full? 198 beq hksw @ yes - key lost, next source 199 200 add r10, r10, #1 @ incremet keystrokes counter 201 str r10, [r9, #BUF_KEYS_CNT] 202 203 ldr r10, [r9, #BUF_TAIL_OFFSET] @ get buffer tail offset 204 @ r8 already contains buffer size 205 cmp r10, r8 @ end of buffer? 206 moveq r10, #0 @ yes - rewind to buffer start 207 208 ldr r12, [r9, #BUF_BUFFER_START] @ get buffer start address 209 add r12, r12, r10, LSL #2 @ calculate buffer tail address 210 ldr r8, [r9, #BUF_KEY] @ get last keycode 211 str r8, [r12] @ append it to the buffer tail 212 213 add r10, r10, #1 @ increment buffer tail offset 214 str r10, [r9, #BUF_TAIL_OFFSET] 215 216 ldr r10, [r9, #BUF_CNT_INT_KEY] @ increment interrupts counter 217 add r10, r10, #1 218 str r10, [r9, #BUF_CNT_INT_KEY] 219 @@@@@@@@@@@@@@@@@@@@@@@@ 220 221 222hksw: @Is hook switch interrupt requested? 223 tst r13, #HOOK_SWITCH_MASK @ is hook switch status bit set? 224 beq mdm @ no - try next source 225 226 227 @@@@@@@@@@@@@@@@@@@@@@@@ 228 @ Hook switch interrupt FIQ mode simple handler 229 230 @ Don't toggle active edge, the switch always bounces 231 232 @ Increment hook switch interrupt counter 233 ldr r10, [r9, #BUF_CNT_INT_HSW] 234 add r10, r10, #1 235 str r10, [r9, #BUF_CNT_INT_HSW] 236 @@@@@@@@@@@@@@@@@@@@@@@@ 237 238 239mdm: @Is it a modem interrupt? 240 tst r13, #MODEM_IRQ_MASK @ is modem status bit set? 241 beq irq @ no - check for next interrupt 242 243 244 @@@@@@@@@@@@@@@@@@@@@@@@ 245 @ Modem FIQ mode interrupt handler stub 246 247 @ Increment modem interrupt counter 248 ldr r10, [r9, #BUF_CNT_INT_MDM] 249 add r10, r10, #1 250 str r10, [r9, #BUF_CNT_INT_MDM] 251 @@@@@@@@@@@@@@@@@@@@@@@@ 252 253 254irq: @ Place deferred_fiq interrupt request 255 ldr r12, deferred_fiq_ih_base @ set pointer to IRQ handler 256 mov r10, #DEFERRED_FIQ_MASK @ set deferred_fiq bit 257 str r10, [r12, #IRQ_ISR_REG_OFFSET] @ place it in the ISR register 258 259 ldr r12, omap1510_gpio_base @ set pointer back to GPIO bank 260 b restart @ check for next GPIO interrupt 261 @@@@@@@@@@@@@@@@@@@@@@@@@@@ 262 263 264/* 265 * Virtual addresses for IO 266 */ 267omap_ih1_base: 268 .word OMAP1_IO_ADDRESS(OMAP_IH1_BASE) 269deferred_fiq_ih_base: 270 .word OMAP1_IO_ADDRESS(DEFERRED_FIQ_IH_BASE) 271omap1510_gpio_base: 272 .word OMAP1_IO_ADDRESS(OMAP1510_GPIO_BASE) 273qwerty_fiqin_end: 274 275/* 276 * Check the size of the FIQ, 277 * it cannot go beyond 0xffff0200, and is copied to 0xffff001c 278 */ 279.if (qwerty_fiqin_end - qwerty_fiqin_start) > (0x200 - 0x1c) 280 .err 281.endif 282