1#ifndef _IOP13XX_IRQS_H_
2#define _IOP13XX_IRQS_H_
3
4#ifndef __ASSEMBLER__
5#include <linux/types.h>
6
7/* INTPND0 CP6 R0 Page 3
8 */
9static inline u32 read_intpnd_0(void)
10{
11	u32 val;
12	asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val));
13	return val;
14}
15
16/* INTPND1 CP6 R1 Page 3
17 */
18static inline u32 read_intpnd_1(void)
19{
20	u32 val;
21	asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val));
22	return val;
23}
24
25/* INTPND2 CP6 R2 Page 3
26 */
27static inline u32 read_intpnd_2(void)
28{
29	u32 val;
30	asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val));
31	return val;
32}
33
34/* INTPND3 CP6 R3 Page 3
35 */
36static inline u32 read_intpnd_3(void)
37{
38	u32 val;
39	asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val));
40	return val;
41}
42#endif
43
44#define INTBASE 0
45#define INTSIZE_4 1
46
47/*
48 * iop34x chipset interrupts
49 */
50#define IOP13XX_IRQ(x)		(IOP13XX_IRQ_OFS + (x))
51
52/*
53 * On IRQ or FIQ register
54 */
55#define IRQ_IOP13XX_ADMA0_EOT	(0)
56#define IRQ_IOP13XX_ADMA0_EOC	(1)
57#define IRQ_IOP13XX_ADMA1_EOT	(2)
58#define IRQ_IOP13XX_ADMA1_EOC	(3)
59#define IRQ_IOP13XX_ADMA2_EOT	(4)
60#define IRQ_IOP13XX_ADMA2_EOC	(5)
61#define IRQ_IOP134_WATCHDOG	(6)
62#define IRQ_IOP13XX_RSVD_7	(7)
63#define IRQ_IOP13XX_TIMER0	(8)
64#define IRQ_IOP13XX_TIMER1	(9)
65#define IRQ_IOP13XX_I2C_0	(10)
66#define IRQ_IOP13XX_I2C_1	(11)
67#define IRQ_IOP13XX_MSG	(12)
68#define IRQ_IOP13XX_MSGIBQ	(13)
69#define IRQ_IOP13XX_ATU_IM	(14)
70#define IRQ_IOP13XX_ATU_BIST	(15)
71#define IRQ_IOP13XX_PPMU	(16)
72#define IRQ_IOP13XX_COREPMU	(17)
73#define IRQ_IOP13XX_CORECACHE	(18)
74#define IRQ_IOP13XX_RSVD_19	(19)
75#define IRQ_IOP13XX_RSVD_20	(20)
76#define IRQ_IOP13XX_RSVD_21	(21)
77#define IRQ_IOP13XX_RSVD_22	(22)
78#define IRQ_IOP13XX_RSVD_23	(23)
79#define IRQ_IOP13XX_XINT0	(24)
80#define IRQ_IOP13XX_XINT1	(25)
81#define IRQ_IOP13XX_XINT2	(26)
82#define IRQ_IOP13XX_XINT3	(27)
83#define IRQ_IOP13XX_XINT4	(28)
84#define IRQ_IOP13XX_XINT5	(29)
85#define IRQ_IOP13XX_XINT6	(30)
86#define IRQ_IOP13XX_XINT7	(31)
87				      /* IINTSRC1 bit */
88#define IRQ_IOP13XX_XINT8	(32)  /* 0  */
89#define IRQ_IOP13XX_XINT9	(33)  /* 1  */
90#define IRQ_IOP13XX_XINT10	(34)  /* 2  */
91#define IRQ_IOP13XX_XINT11	(35)  /* 3  */
92#define IRQ_IOP13XX_XINT12	(36)  /* 4  */
93#define IRQ_IOP13XX_XINT13	(37)  /* 5  */
94#define IRQ_IOP13XX_XINT14	(38)  /* 6  */
95#define IRQ_IOP13XX_XINT15	(39)  /* 7  */
96#define IRQ_IOP13XX_RSVD_40	(40)  /* 8  */
97#define IRQ_IOP13XX_RSVD_41	(41)  /* 9  */
98#define IRQ_IOP13XX_RSVD_42	(42)  /* 10 */
99#define IRQ_IOP13XX_RSVD_43	(43)  /* 11 */
100#define IRQ_IOP13XX_RSVD_44	(44)  /* 12 */
101#define IRQ_IOP13XX_RSVD_45	(45)  /* 13 */
102#define IRQ_IOP13XX_RSVD_46	(46)  /* 14 */
103#define IRQ_IOP13XX_RSVD_47	(47)  /* 15 */
104#define IRQ_IOP13XX_RSVD_48	(48)  /* 16 */
105#define IRQ_IOP13XX_RSVD_49	(49)  /* 17 */
106#define IRQ_IOP13XX_RSVD_50	(50)  /* 18 */
107#define IRQ_IOP13XX_UART0	(51)  /* 19 */
108#define IRQ_IOP13XX_UART1	(52)  /* 20 */
109#define IRQ_IOP13XX_PBIE	(53)  /* 21 */
110#define IRQ_IOP13XX_ATU_CRW	(54)  /* 22 */
111#define IRQ_IOP13XX_ATU_ERR	(55)  /* 23 */
112#define IRQ_IOP13XX_MCU_ERR	(56)  /* 24 */
113#define IRQ_IOP13XX_ADMA0_ERR	(57)  /* 25 */
114#define IRQ_IOP13XX_ADMA1_ERR	(58)  /* 26 */
115#define IRQ_IOP13XX_ADMA2_ERR	(59)  /* 27 */
116#define IRQ_IOP13XX_RSVD_60	(60)  /* 28 */
117#define IRQ_IOP13XX_RSVD_61	(61)  /* 29 */
118#define IRQ_IOP13XX_MSG_ERR	(62)  /* 30 */
119#define IRQ_IOP13XX_RSVD_63	(63)  /* 31 */
120				      /* IINTSRC2 bit */
121#define IRQ_IOP13XX_INTERPROC	(64)  /* 0  */
122#define IRQ_IOP13XX_RSVD_65	(65)  /* 1  */
123#define IRQ_IOP13XX_RSVD_66	(66)  /* 2  */
124#define IRQ_IOP13XX_RSVD_67	(67)  /* 3  */
125#define IRQ_IOP13XX_RSVD_68	(68)  /* 4  */
126#define IRQ_IOP13XX_RSVD_69	(69)  /* 5  */
127#define IRQ_IOP13XX_RSVD_70	(70)  /* 6  */
128#define IRQ_IOP13XX_RSVD_71	(71)  /* 7  */
129#define IRQ_IOP13XX_RSVD_72	(72)  /* 8  */
130#define IRQ_IOP13XX_RSVD_73	(73)  /* 9  */
131#define IRQ_IOP13XX_RSVD_74	(74)  /* 10 */
132#define IRQ_IOP13XX_RSVD_75	(75)  /* 11 */
133#define IRQ_IOP13XX_RSVD_76	(76)  /* 12 */
134#define IRQ_IOP13XX_RSVD_77	(77)  /* 13 */
135#define IRQ_IOP13XX_RSVD_78	(78)  /* 14 */
136#define IRQ_IOP13XX_RSVD_79	(79)  /* 15 */
137#define IRQ_IOP13XX_RSVD_80	(80)  /* 16 */
138#define IRQ_IOP13XX_RSVD_81	(81)  /* 17 */
139#define IRQ_IOP13XX_RSVD_82	(82)  /* 18 */
140#define IRQ_IOP13XX_RSVD_83	(83)  /* 19 */
141#define IRQ_IOP13XX_RSVD_84	(84)  /* 20 */
142#define IRQ_IOP13XX_RSVD_85	(85)  /* 21 */
143#define IRQ_IOP13XX_RSVD_86	(86)  /* 22 */
144#define IRQ_IOP13XX_RSVD_87	(87)  /* 23 */
145#define IRQ_IOP13XX_RSVD_88	(88)  /* 24 */
146#define IRQ_IOP13XX_RSVD_89	(89)  /* 25 */
147#define IRQ_IOP13XX_RSVD_90	(90)  /* 26 */
148#define IRQ_IOP13XX_RSVD_91	(91)  /* 27 */
149#define IRQ_IOP13XX_RSVD_92	(92)  /* 28 */
150#define IRQ_IOP13XX_RSVD_93	(93)  /* 29 */
151#define IRQ_IOP13XX_SIB_ERR	(94)  /* 30 */
152#define IRQ_IOP13XX_SRAM_ERR	(95)  /* 31 */
153				      /* IINTSRC3 bit */
154#define IRQ_IOP13XX_I2C_2	(96)  /* 0  */
155#define IRQ_IOP13XX_ATUE_BIST	(97)  /* 1  */
156#define IRQ_IOP13XX_ATUE_CRW	(98)  /* 2  */
157#define IRQ_IOP13XX_ATUE_ERR	(99)  /* 3  */
158#define IRQ_IOP13XX_IMU	(100) /* 4  */
159#define IRQ_IOP13XX_RSVD_101	(101) /* 5  */
160#define IRQ_IOP13XX_RSVD_102	(102) /* 6  */
161#define IRQ_IOP13XX_TPMI0_OUT	(103) /* 7  */
162#define IRQ_IOP13XX_TPMI1_OUT	(104) /* 8  */
163#define IRQ_IOP13XX_TPMI2_OUT	(105) /* 9  */
164#define IRQ_IOP13XX_TPMI3_OUT	(106) /* 10 */
165#define IRQ_IOP13XX_ATUE_IMA	(107) /* 11 */
166#define IRQ_IOP13XX_ATUE_IMB	(108) /* 12 */
167#define IRQ_IOP13XX_ATUE_IMC	(109) /* 13 */
168#define IRQ_IOP13XX_ATUE_IMD	(110) /* 14 */
169#define IRQ_IOP13XX_MU_MSI_TB	(111) /* 15 */
170#define IRQ_IOP13XX_RSVD_112	(112) /* 16 */
171#define IRQ_IOP13XX_INBD_MSI	(113) /* 17 */
172#define IRQ_IOP13XX_RSVD_114	(114) /* 18 */
173#define IRQ_IOP13XX_RSVD_115	(115) /* 19 */
174#define IRQ_IOP13XX_RSVD_116	(116) /* 20 */
175#define IRQ_IOP13XX_RSVD_117	(117) /* 21 */
176#define IRQ_IOP13XX_RSVD_118	(118) /* 22 */
177#define IRQ_IOP13XX_RSVD_119	(119) /* 23 */
178#define IRQ_IOP13XX_RSVD_120	(120) /* 24 */
179#define IRQ_IOP13XX_RSVD_121	(121) /* 25 */
180#define IRQ_IOP13XX_RSVD_122	(122) /* 26 */
181#define IRQ_IOP13XX_RSVD_123	(123) /* 27 */
182#define IRQ_IOP13XX_RSVD_124	(124) /* 28 */
183#define IRQ_IOP13XX_RSVD_125	(125) /* 29 */
184#define IRQ_IOP13XX_RSVD_126	(126) /* 30 */
185#define IRQ_IOP13XX_HPI	(127) /* 31 */
186
187#ifdef CONFIG_PCI_MSI
188#define IRQ_IOP13XX_MSI_0	(IRQ_IOP13XX_HPI + 1)
189#define NR_IOP13XX_IRQS 	(IRQ_IOP13XX_MSI_0 + 128)
190#else
191#define NR_IOP13XX_IRQS	(IRQ_IOP13XX_HPI + 1)
192#endif
193
194#endif /* _IOP13XX_IRQ_H_ */
195