1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#define VF_UART0_BASE_ADDR	0x40027000
11#define VF_UART1_BASE_ADDR	0x40028000
12#define VF_UART2_BASE_ADDR	0x40029000
13#define VF_UART3_BASE_ADDR	0x4002a000
14#define VF_UART_BASE_ADDR(n)	VF_UART##n##_BASE_ADDR
15#define VF_UART_BASE(n)		VF_UART_BASE_ADDR(n)
16#define VF_UART_PHYSICAL_BASE	VF_UART_BASE(CONFIG_DEBUG_VF_UART_PORT)
17
18#define VF_UART_VIRTUAL_BASE	0xfe000000
19
20	.macro	addruart, rp, rv, tmp
21	ldr	\rp, =VF_UART_PHYSICAL_BASE 	@ physical
22	and	\rv, \rp, #0xffffff		@ offset within 16MB section
23	add	\rv, \rv, #VF_UART_VIRTUAL_BASE
24	.endm
25
26	.macro	senduart, rd, rx
27	strb	\rd, [\rx, #0x7]	@ Data Register
28	.endm
29
30	.macro	busyuart, rd, rx
311001:	ldrb	\rd, [\rx, #0x4]	@ Status Register 1
32	tst	\rd, #1 << 6		@ TC
33	beq	1001b			@ wait until transmit done
34	.endm
35
36	.macro	waituart,rd,rx
37	.endm
38