1ARM Virtual Generic Interrupt Controller (VGIC)
2===============================================
3
4Device types supported:
5  KVM_DEV_TYPE_ARM_VGIC_V2     ARM Generic Interrupt Controller v2.0
6  KVM_DEV_TYPE_ARM_VGIC_V3     ARM Generic Interrupt Controller v3.0
7
8Only one VGIC instance may be instantiated through either this API or the
9legacy KVM_CREATE_IRQCHIP api.  The created VGIC will act as the VM interrupt
10controller, requiring emulated user-space devices to inject interrupts to the
11VGIC instead of directly to CPUs.
12
13Creating a guest GICv3 device requires a host GICv3 as well.
14GICv3 implementations with hardware compatibility support allow a guest GICv2
15as well.
16
17Groups:
18  KVM_DEV_ARM_VGIC_GRP_ADDR
19  Attributes:
20    KVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit)
21      Base address in the guest physical address space of the GIC distributor
22      register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2.
23      This address needs to be 4K aligned and the region covers 4 KByte.
24
25    KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit)
26      Base address in the guest physical address space of the GIC virtual cpu
27      interface register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2.
28      This address needs to be 4K aligned and the region covers 4 KByte.
29
30    KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
31      Base address in the guest physical address space of the GICv3 distributor
32      register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
33      This address needs to be 64K aligned and the region covers 64 KByte.
34
35    KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
36      Base address in the guest physical address space of the GICv3
37      redistributor register mappings. There are two 64K pages for each
38      VCPU and all of the redistributor pages are contiguous.
39      Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
40      This address needs to be 64K aligned.
41
42
43  KVM_DEV_ARM_VGIC_GRP_DIST_REGS
44  Attributes:
45    The attr field of kvm_device_attr encodes two values:
46    bits:     | 63   ....  40 | 39 ..  32  |  31   ....    0 |
47    values:   |    reserved   |   cpu id   |      offset     |
48
49    All distributor regs are (rw, 32-bit)
50
51    The offset is relative to the "Distributor base address" as defined in the
52    GICv2 specs.  Getting or setting such a register has the same effect as
53    reading or writing the register on the actual hardware from the cpu
54    specified with cpu id field.  Note that most distributor fields are not
55    banked, but return the same value regardless of the cpu id used to access
56    the register.
57  Limitations:
58    - Priorities are not implemented, and registers are RAZ/WI
59    - Currently only implemented for KVM_DEV_TYPE_ARM_VGIC_V2.
60  Errors:
61    -ENODEV: Getting or setting this register is not yet supported
62    -EBUSY: One or more VCPUs are running
63
64  KVM_DEV_ARM_VGIC_GRP_CPU_REGS
65  Attributes:
66    The attr field of kvm_device_attr encodes two values:
67    bits:     | 63   ....  40 | 39 ..  32  |  31   ....    0 |
68    values:   |    reserved   |   cpu id   |      offset     |
69
70    All CPU interface regs are (rw, 32-bit)
71
72    The offset specifies the offset from the "CPU interface base address" as
73    defined in the GICv2 specs.  Getting or setting such a register has the
74    same effect as reading or writing the register on the actual hardware.
75
76    The Active Priorities Registers APRn are implementation defined, so we set a
77    fixed format for our implementation that fits with the model of a "GICv2
78    implementation without the security extensions" which we present to the
79    guest.  This interface always exposes four register APR[0-3] describing the
80    maximum possible 128 preemption levels.  The semantics of the register
81    indicate if any interrupts in a given preemption level are in the active
82    state by setting the corresponding bit.
83
84    Thus, preemption level X has one or more active interrupts if and only if:
85
86      APRn[X mod 32] == 0b1,  where n = X / 32
87
88    Bits for undefined preemption levels are RAZ/WI.
89
90  Limitations:
91    - Priorities are not implemented, and registers are RAZ/WI
92    - Currently only implemented for KVM_DEV_TYPE_ARM_VGIC_V2.
93  Errors:
94    -ENODEV: Getting or setting this register is not yet supported
95    -EBUSY: One or more VCPUs are running
96
97  KVM_DEV_ARM_VGIC_GRP_NR_IRQS
98  Attributes:
99    A value describing the number of interrupts (SGI, PPI and SPI) for
100    this GIC instance, ranging from 64 to 1024, in increments of 32.
101
102  Errors:
103    -EINVAL: Value set is out of the expected range
104    -EBUSY: Value has already be set, or GIC has already been initialized
105            with default values.
106
107  KVM_DEV_ARM_VGIC_GRP_CTRL
108  Attributes:
109    KVM_DEV_ARM_VGIC_CTRL_INIT
110      request the initialization of the VGIC, no additional parameter in
111      kvm_device_attr.addr.
112  Errors:
113    -ENXIO: VGIC not properly configured as required prior to calling
114     this attribute
115    -ENODEV: no online VCPU
116    -ENOMEM: memory shortage when allocating vgic internal data
117