1QCOM GSBI (General Serial Bus Interface) Driver
2
3The GSBI controller is modeled as a node with zero or more child nodes, each
4representing a serial sub-node device that is mux'd as part of the GSBI
5configuration settings.  The mode setting will govern the input/output mode of
6the 4 GSBI IOs.
7
8Required properties:
9- compatible:	Should contain "qcom,gsbi-v1.0.0"
10- cell-index:	Should contain the GSBI index
11- reg: Address range for GSBI registers
12- clocks: required clock
13- clock-names: must contain "iface" entry
14- qcom,mode : indicates MUX value for configuration of the serial interface.
15  Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values.
16
17Optional properties:
18- qcom,crci : indicates CRCI MUX value for QUP CRCI ports.  Please reference
19  dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
20- syscon-tcsr: indicates phandle of TCSR syscon node.  Required if child uses
21  dma.
22
23Required properties if child node exists:
24- #address-cells: Must be 1
25- #size-cells: Must be 1
26- ranges: Must be present
27
28Properties for children:
29
30A GSBI controller node can contain 0 or more child nodes representing serial
31devices.  These serial devices can be a QCOM UART, I2C controller, spi
32controller, or some combination of aforementioned devices.
33
34See the following for child node definitions:
35Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt
36Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
37Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
38
39Example for APQ8064:
40
41#include <dt-bindings/soc/qcom,gsbi.h>
42
43	gsbi4@16300000 {
44		compatible = "qcom,gsbi-v1.0.0";
45		cell-index = <4>;
46		reg = <0x16300000 0x100>;
47		clocks = <&gcc GSBI4_H_CLK>;
48		clock-names = "iface";
49		#address-cells = <1>;
50		#size-cells = <1>;
51		ranges;
52		qcom,mode = <GSBI_PROT_I2C_UART>;
53		qcom,crci = <GSBI_CRCI_QUP>;
54
55		syscon-tcsr = <&tcsr>;
56
57		/* child nodes go under here */
58
59		i2c_qup4: i2c@16380000 {
60			compatible = "qcom,i2c-qup-v1.1.1";
61			reg = <0x16380000 0x1000>;
62			interrupts = <0 153 0>;
63
64			clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
65			clock-names = "core", "iface";
66
67			clock-frequency = <200000>;
68
69			#address-cells = <1>;
70			#size-cells = <0>;
71
72		};
73
74		uart4:	serial@16340000 {
75			compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
76			reg = <0x16340000 0x1000>,
77				<0x16300000 0x1000>;
78			interrupts = <0 152 0x0>;
79			clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
80			clock-names = "core", "iface";
81			status = "ok";
82		};
83	};
84
85	tcsr: syscon@1a400000 {
86		compatible = "qcom,apq8064-tcsr", "syscon";
87		reg = <0x1a400000 0x100>;
88	};
89