1* Marvell Armada 375 SoC pinctrl driver for mpp 2 3Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding 4part and usage. 5 6Required properties: 7- compatible: "marvell,88f6720-pinctrl" 8- reg: register specifier of MPP registers 9 10Available mpp pins/groups and functions: 11Note: brackets (x) are not part of the mpp name for marvell,function and given 12only for more detailed description in this document. 13 14name pins functions 15================================================================================ 16mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1) 17mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi) 18mpp2 2 gpio, dev(ad4), ptp(eventreq), led(c0), audio(sdi) 19mpp3 3 gpio, dev(ad5), ptp(triggen), led(p3), audio(mclk) 20mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso) 21mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2) 22mpp6 6 gpio, dev(ad0), led(p1), audio(rclk) 23mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk) 24mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0) 25mpp9 9 gpio, spi0(sck), spi1(sck), nand(we) 26mpp10 10 gpio, dram(vttctrl), led(c1), nand(re) 27mpp11 11 gpio, dev(a0), led(c2), audio(sdo) 28mpp12 12 gpio, dev(a1), audio(bclk) 29mpp13 13 gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn) 30mpp14 14 gpio, i2c0(sda), uart1(txd) 31mpp15 15 gpio, i2c0(sck), uart1(rxd) 32mpp16 16 gpio, uart0(txd) 33mpp17 17 gpio, uart0(rxd) 34mpp18 18 gpio, tdm(intn) 35mpp19 19 gpio, tdm(rstn) 36mpp20 20 gpio, tdm(pclk) 37mpp21 21 gpio, tdm(fsync) 38mpp22 22 gpio, tdm(drx) 39mpp23 23 gpio, tdm(dtx) 40mpp24 24 gpio, led(p0), ge1(rxd0), sd(cmd), uart0(rts) 41mpp25 25 gpio, led(p2), ge1(rxd1), sd(d0), uart0(cts) 42mpp26 26 gpio, pcie0(clkreq), ge1(rxd2), sd(d2), uart1(rts) 43mpp27 27 gpio, pcie1(clkreq), ge1(rxd3), sd(d1), uart1(cts) 44mpp28 28 gpio, led(p3), ge1(txctl), sd(clk) 45mpp29 29 gpio, pcie1(clkreq), ge1(rxclk), sd(d3) 46mpp30 30 gpio, ge1(txd0), spi1(cs0) 47mpp31 31 gpio, ge1(txd1), spi1(mosi) 48mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(triggen) 49mpp33 33 gpio, ge1(txd3), spi1(miso) 50mpp34 34 gpio, ge1(txclkout), spi1(sck) 51mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2) 52mpp36 36 gpio, pcie0(clkreq) 53mpp37 37 gpio, pcie0(clkreq), tdm(intn), ge(mdc) 54mpp38 38 gpio, pcie1(clkreq), ge(mdio) 55mpp39 39 gpio, ref(clkout) 56mpp40 40 gpio, uart1(txd) 57mpp41 41 gpio, uart1(rxd) 58mpp42 42 gpio, spi1(cs2), led(c0) 59mpp43 43 gpio, sata0(prsnt), dram(vttctrl) 60mpp44 44 gpio, sata0(prsnt) 61mpp45 45 gpio, spi0(cs2), pcie0(rstoutn) 62mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0) 63mpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1) 64mpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2) 65mpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3) 66mpp50 50 gpio, led(c0), ge0(rxd0), ge1(rxd0) 67mpp51 51 gpio, led(c1), ge0(rxd1), ge1(rxd1) 68mpp52 52 gpio, led(c2), ge0(rxd2), ge1(rxd2) 69mpp53 53 gpio, pcie1(rstoutn), ge0(rxd3), ge1(rxd3) 70mpp54 54 gpio, pcie0(rstoutn), ge0(rxctl), ge1(rxctl) 71mpp55 55 gpio, ge0(rxclk), ge1(rxclk) 72mpp56 56 gpio, ge0(txclkout), ge1(txclkout) 73mpp57 57 gpio, ge0(txctl), ge1(txctl) 74mpp58 58 gpio, led(c0) 75mpp59 59 gpio, led(c1) 76mpp60 60 gpio, uart1(txd), led(c2) 77mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0) 78mpp62 62 gpio, i2c1(sck), led(p1) 79mpp63 63 gpio, ptp(triggen), led(p2) 80mpp64 64 gpio, dram(vttctrl), led(p3) 81mpp65 65 gpio, sata1(prsnt) 82mpp66 66 gpio, ptp(eventreq), spi1(cs3) 83