1NVIDIA Tegra Memory Controller device tree bindings
2===================================================
3
4Required properties:
5- compatible: Should be "nvidia,tegra<chip>-mc"
6- reg: Physical base address and length of the controller's registers.
7- clocks: Must contain an entry for each entry in clock-names.
8  See ../clocks/clock-bindings.txt for details.
9- clock-names: Must include the following entries:
10  - mc: the module's clock input
11- interrupts: The interrupt outputs from the controller.
12- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines
13  the SWGROUP of the master.
14
15This device implements an IOMMU that complies with the generic IOMMU binding.
16See ../iommu/iommu.txt for details.
17
18Example:
19--------
20
21	mc: memory-controller@0,70019000 {
22		compatible = "nvidia,tegra124-mc";
23		reg = <0x0 0x70019000 0x0 0x1000>;
24		clocks = <&tegra_car TEGRA124_CLK_MC>;
25		clock-names = "mc";
26
27		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
28
29		#iommu-cells = <1>;
30	};
31
32	sdhci@0,700b0000 {
33		compatible = "nvidia,tegra124-sdhci";
34		...
35		iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;
36	};
37