1Chips&Media Coda multi-standard codec IP
2========================================
3
4Coda codec IPs are present in i.MX SoCs in various versions,
5called VPU (Video Processing Unit).
6
7Required properties:
8- compatible : should be "fsl,<chip>-src" for i.MX SoCs:
9  (a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27
10  (b) "fsl,imx53-vpu" for CODA7541 present in i.MX53
11  (c) "fsl,imx6q-vpu" for CODA960 present in i.MX6q
12- reg: should be register base and length as documented in the
13  SoC reference manual
14- interrupts : Should contain the VPU interrupt. For CODA960,
15  a second interrupt is needed for the MJPEG unit.
16- clocks : Should contain the ahb and per clocks, in the order
17  determined by the clock-names property.
18- clock-names : Should be "ahb", "per"
19- iram : phandle pointing to the SRAM device node
20
21Example:
22
23vpu: vpu@63ff4000 {
24	compatible = "fsl,imx53-vpu";
25	reg = <0x63ff4000 0x1000>;
26	interrupts = <9>;
27	clocks = <&clks 63>, <&clks 63>;
28	clock-names = "ahb", "per";
29	iram = <&ocram>;
30};
31