1Device-Tree bindings for LVDS Display Bridge (ldb)
2
3LVDS Display Bridge
4===================
5
6The LVDS Display Bridge device tree node contains up to two lvds-channel
7nodes describing each of the two LVDS encoder channels of the bridge.
8
9Required properties:
10 - #address-cells : should be <1>
11 - #size-cells : should be <0>
12 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
13                Both LDB versions are similar, but i.MX6 has an additional
14                multiplexer in the front to select any of the four IPU display
15                interfaces as input for each LVDS channel.
16 - gpr : should be <&gpr> on i.MX53 and i.MX6q.
17         The phandle points to the iomuxc-gpr region containing the LVDS
18         control register.
19- clocks, clock-names : phandles to the LDB divider and selector clocks and to
20                        the display interface selector clocks, as described in
21                        Documentation/devicetree/bindings/clock/clock-bindings.txt
22        The following clocks are expected on i.MX53:
23                "di0_pll" - LDB LVDS channel 0 mux
24                "di1_pll" - LDB LVDS channel 1 mux
25                "di0" - LDB LVDS channel 0 gate
26                "di1" - LDB LVDS channel 1 gate
27                "di0_sel" - IPU1 DI0 mux
28                "di1_sel" - IPU1 DI1 mux
29        On i.MX6q the following additional clocks are needed:
30                "di2_sel" - IPU2 DI0 mux
31                "di3_sel" - IPU2 DI1 mux
32        The needed clock numbers for each are documented in
33        Documentation/devicetree/bindings/clock/imx5-clock.txt, and in
34        Documentation/devicetree/bindings/clock/imx6q-clock.txt.
35
36Optional properties:
37 - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q
38 - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53,
39               not used on i.MX6q
40 - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should
41   be configured - one input will be distributed on both outputs in dual
42   channel mode
43
44LVDS Channel
45============
46
47Each LVDS Channel has to contain either an of graph link to a panel device node
48or a display-timings node that describes the video timings for the connected
49LVDS display as well as the fsl,data-mapping and fsl,data-width properties.
50
51Required properties:
52 - reg : should be <0> or <1>
53 - port: Input and output port nodes with endpoint definitions as defined in
54   Documentation/devicetree/bindings/graph.txt.
55   On i.MX5, the internal two-input-multiplexer is used. Due to hardware
56   limitations, only one input port (port@[0,1]) can be used for each channel
57   (lvds-channel@[0,1], respectively).
58   On i.MX6, there should be four input ports (port@[0-3]) that correspond
59   to the four LVDS multiplexer inputs.
60   A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected
61   to a panel input port. Optionally, the output port can be left out if
62   display-timings are used instead.
63
64Optional properties (required if display-timings are used):
65 - display-timings : A node that describes the display timings as defined in
66   Documentation/devicetree/bindings/video/display-timing.txt.
67 - fsl,data-mapping : should be "spwg" or "jeida"
68                      This describes how the color bits are laid out in the
69                      serialized LVDS signal.
70 - fsl,data-width : should be <18> or <24>
71
72example:
73
74gpr: iomuxc-gpr@53fa8000 {
75	/* ... */
76};
77
78ldb: ldb@53fa8008 {
79	#address-cells = <1>;
80	#size-cells = <0>;
81	compatible = "fsl,imx53-ldb";
82	gpr = <&gpr>;
83	clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
84		 <&clks IMX5_CLK_LDB_DI1_SEL>,
85		 <&clks IMX5_CLK_IPU_DI0_SEL>,
86		 <&clks IMX5_CLK_IPU_DI1_SEL>,
87		 <&clks IMX5_CLK_LDB_DI0_GATE>,
88		 <&clks IMX5_CLK_LDB_DI1_GATE>;
89	clock-names = "di0_pll", "di1_pll",
90		      "di0_sel", "di1_sel",
91		      "di0", "di1";
92
93	/* Using an of-graph endpoint link to connect the panel */
94	lvds-channel@0 {
95		#address-cells = <1>;
96		#size-cells = <0>;
97		reg = <0>;
98
99		port@0 {
100			reg = <0>;
101
102			lvds0_in: endpoint {
103				remote-endpoint = <&ipu_di0_lvds0>;
104			};
105		};
106
107		port@2 {
108			reg = <2>;
109
110			lvds0_out: endpoint {
111				remote-endpoint = <&panel_in>;
112			};
113		};
114	};
115
116	/* Using display-timings and fsl,data-mapping/width instead */
117	lvds-channel@1 {
118		#address-cells = <1>;
119		#size-cells = <0>;
120		reg = <1>;
121		fsl,data-mapping = "spwg";
122		fsl,data-width = <24>;
123
124		display-timings {
125			/* ... */
126		};
127
128		port@1 {
129			reg = <1>;
130
131			lvds1_in: endpoint {
132				remote-endpoint = <&ipu_di1_lvds1>;
133			};
134		};
135	};
136};
137
138panel: lvds-panel {
139	/* ... */
140
141	port {
142		panel_in: endpoint {
143			remote-endpoint = <&lvds0_out>;
144		};
145	};
146};
147