1* Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
2
3Required properties:
4- compatible : Should be one of
5      "fsl,imx25-sdma"
6      "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma"
7      "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma"
8      "fsl,imx51-sdma"
9      "fsl,imx53-sdma"
10      "fsl,imx6q-sdma"
11  The -to variants should be preferred since they allow to determine the
12  correct ROM script addresses needed for the driver to work without additional
13  firmware.
14- reg : Should contain SDMA registers location and length
15- interrupts : Should contain SDMA interrupt
16- #dma-cells : Must be <3>.
17  The first cell specifies the DMA request/event ID.  See details below
18  about the second and third cell.
19- fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
20  scripts firmware
21
22The second cell of dma phandle specifies the peripheral type of DMA transfer.
23The full ID of peripheral types can be found below.
24
25	ID	transfer type
26	---------------------
27	0	MCU domain SSI
28	1	Shared SSI
29	2	MMC
30	3	SDHC
31	4	MCU domain UART
32	5	Shared UART
33	6	FIRI
34	7	MCU domain CSPI
35	8	Shared CSPI
36	9	SIM
37	10	ATA
38	11	CCM
39	12	External peripheral
40	13	Memory Stick Host Controller
41	14	Shared Memory Stick Host Controller
42	15	DSP
43	16	Memory
44	17	FIFO type Memory
45	18	SPDIF
46	19	IPU Memory
47	20	ASRC
48	21	ESAI
49	22	SSI Dual FIFO	(needs firmware ver >= 2)
50	23	Shared ASRC
51	24	SAI
52
53The third cell specifies the transfer priority as below.
54
55	ID	transfer priority
56	-------------------------
57	0	High
58	1	Medium
59	2	Low
60
61Examples:
62
63sdma@83fb0000 {
64	compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
65	reg = <0x83fb0000 0x4000>;
66	interrupts = <6>;
67	#dma-cells = <3>;
68	fsl,sdma-ram-script-name = "sdma-imx51.bin";
69};
70
71DMA clients connected to the i.MX SDMA controller must use the format
72described in the dma.txt file.
73
74Examples:
75
76ssi2: ssi@70014000 {
77	compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
78	reg = <0x70014000 0x4000>;
79	interrupts = <30>;
80	clocks = <&clks 49>;
81	dmas = <&sdma 24 1 0>,
82	       <&sdma 25 1 0>;
83	dma-names = "rx", "tx";
84	fsl,fifo-depth = <15>;
85};
86