1<html><head><meta http-equiv="Content-Type" content="text/html; charset=ANSI_X3.4-1968"><title>Chapter 5. Configuring And Activating The Port</title><meta name="generator" content="DocBook XSL Stylesheets V1.78.1"><link rel="home" href="index.html" title="Z8530 Programming Guide"><link rel="up" href="index.html" title="Z8530 Programming Guide"><link rel="prev" href="Attaching_Network_Interfaces.html" title="Chapter 4. Attaching Network Interfaces"><link rel="next" href="Network_Layer_Functions.html" title="Chapter 6. Network Layer Functions"></head><body bgcolor="white" text="black" link="#0000FF" vlink="#840084" alink="#0000FF"><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 5. Configuring And Activating The Port</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="Attaching_Network_Interfaces.html">Prev</a> </td><th width="60%" align="center"> </th><td width="20%" align="right"> <a accesskey="n" href="Network_Layer_Functions.html">Next</a></td></tr></table><hr></div><div class="chapter"><div class="titlepage"><div><div><h1 class="title"><a name="Configuring_And_Activating_The_Port"></a>Chapter 5. Configuring And Activating The Port</h1></div></div></div><p> 2 The Z85230 driver provides helper functions and tables to load the 3 port registers on the Z8530 chips. When programming the register 4 settings for a channel be aware that the documentation recommends 5 initialisation orders. Strange things happen when these are not 6 followed. 7 </p><p> 8 <code class="function">z8530_channel_load</code> takes an array of 9 pairs of initialisation values in an array of u8 type. The first 10 value is the Z8530 register number. Add 16 to indicate the alternate 11 register bank on the later chips. The array is terminated by a 255. 12 </p><p> 13 The driver provides a pair of public tables. The 14 z8530_hdlc_kilostream table is for the UK 'Kilostream' service and 15 also happens to cover most other end host configurations. The 16 z8530_hdlc_kilostream_85230 table is the same configuration using 17 the enhancements of the 85230 chip. The configuration loaded is 18 standard NRZ encoded synchronous data with HDLC bitstuffing. All 19 of the timing is taken from the other end of the link. 20 </p><p> 21 When writing your own tables be aware that the driver internally 22 tracks register values. It may need to reload values. You should 23 therefore be sure to set registers 1-7, 9-11, 14 and 15 in all 24 configurations. Where the register settings depend on DMA selection 25 the driver will update the bits itself when you open or close. 26 Loading a new table with the interface open is not recommended. 27 </p><p> 28 There are three standard configurations supported by the core 29 code. In PIO mode the interface is programmed up to use 30 interrupt driven PIO. This places high demands on the host processor 31 to avoid latency. The driver is written to take account of latency 32 issues but it cannot avoid latencies caused by other drivers, 33 notably IDE in PIO mode. Because the drivers allocate buffers you 34 must also prevent MTU changes while the port is open. 35 </p><p> 36 Once the port is open it will call the rx_function of each channel 37 whenever a completed packet arrived. This is invoked from 38 interrupt context and passes you the channel and a network 39 buffer (struct sk_buff) holding the data. The data includes 40 the CRC bytes so most users will want to trim the last two 41 bytes before processing the data. This function is very timing 42 critical. When you wish to simply discard data the support 43 code provides the function <code class="function">z8530_null_rx</code> 44 to discard the data. 45 </p><p> 46 To active PIO mode sending and receiving the <code class="function"> 47 z8530_sync_open</code> is called. This expects to be passed 48 the network device and the channel. Typically this is called from 49 your network device open callback. On a failure a non zero error 50 status is returned. The <code class="function">z8530_sync_close</code> 51 function shuts down a PIO channel. This must be done before the 52 channel is opened again and before the driver shuts down 53 and unloads. 54 </p><p> 55 The ideal mode of operation is dual channel DMA mode. Here the 56 kernel driver will configure the board for DMA in both directions. 57 The driver also handles ISA DMA issues such as controller 58 programming and the memory range limit for you. This mode is 59 activated by calling the <code class="function">z8530_sync_dma_open</code> 60 function. On failure a non zero error value is returned. 61 Once this mode is activated it can be shut down by calling the 62 <code class="function">z8530_sync_dma_close</code>. You must call the close 63 function matching the open mode you used. 64 </p><p> 65 The final supported mode uses a single DMA channel to drive the 66 transmit side. As the Z85C30 has a larger FIFO on the receive 67 channel this tends to increase the maximum speed a little. 68 This is activated by calling the <code class="function">z8530_sync_txdma_open 69 </code>. This returns a non zero error code on failure. The 70 <code class="function">z8530_sync_txdma_close</code> function closes down 71 the Z8530 interface from this mode. 72 </p></div><div class="navfooter"><hr><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="Attaching_Network_Interfaces.html">Prev</a> </td><td width="20%" align="center"> </td><td width="40%" align="right"> <a accesskey="n" href="Network_Layer_Functions.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Chapter 4. Attaching Network Interfaces </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> Chapter 6. Network Layer Functions</td></tr></table></div></body></html> 73