1<html><head><meta http-equiv="Content-Type" content="text/html; charset=ANSI_X3.4-1968"><title>struct irq_chip_generic</title><meta name="generator" content="DocBook XSL Stylesheets V1.78.1"><link rel="home" href="index.html" title="Linux generic IRQ handling"><link rel="up" href="structs.html" title="Chapter 8. Structures"><link rel="prev" href="API-struct-irq-chip-type.html" title="struct irq_chip_type"><link rel="next" href="API-enum-irq-gc-flags.html" title="enum irq_gc_flags"></head><body bgcolor="white" text="black" link="#0000FF" vlink="#840084" alink="#0000FF"><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center"><span class="phrase">struct irq_chip_generic</span></th></tr><tr><td width="20%" align="left"><a accesskey="p" href="API-struct-irq-chip-type.html">Prev</a> </td><th width="60%" align="center">Chapter 8. Structures</th><td width="20%" align="right"> <a accesskey="n" href="API-enum-irq-gc-flags.html">Next</a></td></tr></table><hr></div><div class="refentry"><a name="API-struct-irq-chip-generic"></a><div class="titlepage"></div><div class="refnamediv"><h2>Name</h2><p>struct irq_chip_generic — 2 Generic irq chip data structure 3 </p></div><div class="refsynopsisdiv"><h2>Synopsis</h2><pre class="programlisting"> 4struct irq_chip_generic { 5 raw_spinlock_t lock; 6 void __iomem * reg_base; 7 u32 (* reg_readl) (void __iomem *addr); 8 void (* reg_writel) (u32 val, void __iomem *addr); 9 unsigned int irq_base; 10 unsigned int irq_cnt; 11 u32 mask_cache; 12 u32 type_cache; 13 u32 polarity_cache; 14 u32 wake_enabled; 15 u32 wake_active; 16 unsigned int num_ct; 17 void * private; 18 unsigned long installed; 19 unsigned long unused; 20 struct irq_domain * domain; 21 struct list_head list; 22 struct irq_chip_type chip_types[0]; 23}; </pre></div><div class="refsect1"><a name="idp1103024172"></a><h2>Members</h2><div class="variablelist"><dl class="variablelist"><dt><span class="term">lock</span></dt><dd><p> 24 Lock to protect register and cache data access 25 </p></dd><dt><span class="term">reg_base</span></dt><dd><p> 26 Register base address (virtual) 27 </p></dd><dt><span class="term">reg_readl</span></dt><dd><p> 28 Alternate I/O accessor (defaults to readl if NULL) 29 </p></dd><dt><span class="term">reg_writel</span></dt><dd><p> 30 Alternate I/O accessor (defaults to writel if NULL) 31 </p></dd><dt><span class="term">irq_base</span></dt><dd><p> 32 Interrupt base nr for this chip 33 </p></dd><dt><span class="term">irq_cnt</span></dt><dd><p> 34 Number of interrupts handled by this chip 35 </p></dd><dt><span class="term">mask_cache</span></dt><dd><p> 36 Cached mask register shared between all chip types 37 </p></dd><dt><span class="term">type_cache</span></dt><dd><p> 38 Cached type register 39 </p></dd><dt><span class="term">polarity_cache</span></dt><dd><p> 40 Cached polarity register 41 </p></dd><dt><span class="term">wake_enabled</span></dt><dd><p> 42 Interrupt can wakeup from suspend 43 </p></dd><dt><span class="term">wake_active</span></dt><dd><p> 44 Interrupt is marked as an wakeup from suspend source 45 </p></dd><dt><span class="term">num_ct</span></dt><dd><p> 46 Number of available irq_chip_type instances (usually 1) 47 </p></dd><dt><span class="term">private</span></dt><dd><p> 48 Private data for non generic chip callbacks 49 </p></dd><dt><span class="term">installed</span></dt><dd><p> 50 bitfield to denote installed interrupts 51 </p></dd><dt><span class="term">unused</span></dt><dd><p> 52 bitfield to denote unused interrupts 53 </p></dd><dt><span class="term">domain</span></dt><dd><p> 54 irq domain pointer 55 </p></dd><dt><span class="term">list</span></dt><dd><p> 56 List head for keeping track of instances 57 </p></dd><dt><span class="term">chip_types[0]</span></dt><dd><p> 58 Array of interrupt irq_chip_types 59 </p></dd></dl></div></div><div class="refsect1"><a name="idp1103037316"></a><h2>Description</h2><p> 60 Note, that irq_chip_generic can have multiple irq_chip_type 61 implementations which can be associated to a particular irq line of 62 an irq_chip_generic instance. That allows to share and protect 63 state in an irq_chip_generic instance when we need to implement 64 different flow mechanisms (level/edge) for it. 65</p></div></div><div class="navfooter"><hr><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="API-struct-irq-chip-type.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="structs.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="API-enum-irq-gc-flags.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top"><span class="phrase">struct irq_chip_type</span> </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> <span class="phrase">enum irq_gc_flags</span></td></tr></table></div></body></html> 66