1<html><head><meta http-equiv="Content-Type" content="text/html; charset=ANSI_X3.4-1968"><title>Chapter 4. drm/i915 Intel GFX Driver</title><meta name="generator" content="DocBook XSL Stylesheets V1.78.1"><link rel="home" href="index.html" title="Linux DRM Developer's Guide"><link rel="up" href="drmDrivers.html" title="Part II. DRM Drivers"><link rel="prev" href="drmDrivers.html" title="Part II. DRM Drivers"><link rel="next" href="API---intel-display-power-is-enabled.html" title="__intel_display_power_is_enabled"></head><body bgcolor="white" text="black" link="#0000FF" vlink="#840084" alink="#0000FF"><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 4. drm/i915 Intel GFX Driver</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="drmDrivers.html">Prev</a> </td><th width="60%" align="center">Part II. DRM Drivers</th><td width="20%" align="right"> <a accesskey="n" href="API---intel-display-power-is-enabled.html">Next</a></td></tr></table><hr></div><div class="chapter"><div class="titlepage"><div><div><h2 class="title"><a name="drmI915"></a>Chapter 4. drm/i915 Intel GFX Driver</h2></div></div></div><div class="toc"><p><b>Table of Contents</b></p><dl class="toc"><dt><span class="sect1"><a href="drmI915.html#idp1127682964">Core Driver Infrastructure</a></span></dt><dd><dl><dt><span class="sect2"><a href="drmI915.html#idp1127683628">Runtime Power Management</a></span></dt><dt><span class="sect2"><a href="drmI915.html#idp1127820844">Interrupt Handling</a></span></dt><dt><span class="sect2"><a href="drmI915.html#idp1127853244">Intel GVT-g Guest Support(vGPU)</a></span></dt></dl></dd><dt><span class="sect1"><a href="ch04s02.html">Display Hardware Handling</a></span></dt><dd><dl><dt><span class="sect2"><a href="ch04s02.html#idp1127882228">Mode Setting Infrastructure</a></span></dt><dt><span class="sect2"><a href="ch04s02.html#idp1127883116">Frontbuffer Tracking</a></span></dt><dt><span class="sect2"><a href="ch04s02.html#idp1127966068">Display FIFO Underrun Reporting</a></span></dt><dt><span class="sect2"><a href="ch04s02.html#idp1128014948">Plane Configuration</a></span></dt><dt><span class="sect2"><a href="ch04s02.html#idp1128015892">Atomic Plane Helpers</a></span></dt><dt><span class="sect2"><a href="ch04s02.html#idp1128065636">Output Probing</a></span></dt><dt><span class="sect2"><a href="ch04s02.html#idp1128066516">High Definition Audio</a></span></dt><dt><span class="sect2"><a href="ch04s02.html#idp1128104188">Panel Self Refresh PSR (PSR/SRD)</a></span></dt><dt><span class="sect2"><a href="ch04s02.html#idp1128147260">Frame Buffer Compression (FBC)</a></span></dt><dt><span class="sect2"><a href="ch04s02.html#idp1128179172">Display Refresh Rate Switching (DRRS)</a></span></dt><dt><span class="sect2"><a href="ch04s02.html#idp1128232364">DPIO</a></span></dt></dl></dd><dt><span class="sect1"><a href="ch04s03.html">Memory Management and Command Submission</a></span></dt><dd><dl><dt><span class="sect2"><a href="ch04s03.html#idp1128258212">Batchbuffer Parsing</a></span></dt><dt><span class="sect2"><a href="ch04s03.html#idp1128310204">Batchbuffer Pools</a></span></dt><dt><span class="sect2"><a href="ch04s03.html#idp1128337188">Logical Rings, Logical Ring Contexts and Execlists</a></span></dt><dt><span class="sect2"><a href="ch04s03.html#idp1128435628">Global GTT views</a></span></dt><dt><span class="sect2"><a href="ch04s03.html#idp1128473508">Buffer Object Eviction</a></span></dt><dt><span class="sect2"><a href="ch04s03.html#idp1128510940">Buffer Object Memory Shrinking</a></span></dt></dl></dd><dt><span class="sect1"><a href="ch04s04.html"> Tracing </a></span></dt><dd><dl><dt><span class="sect2"><a href="ch04s04.html#idp1128541092"> i915_ppgtt_create and i915_ppgtt_release </a></span></dt><dt><span class="sect2"><a href="ch04s04.html#idp1128542276"> i915_context_create and i915_context_free </a></span></dt><dt><span class="sect2"><a href="ch04s04.html#idp1128543204"> switch_mm </a></span></dt></dl></dd></dl></div><p> 2 The drm/i915 driver supports all (with the exception of some very early 3 models) integrated GFX chipsets with both Intel display and rendering 4 blocks. This excludes a set of SoC platforms with an SGX rendering unit, 5 those have basic support through the gma500 drm driver. 6 </p><div class="sect1"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="idp1127682964"></a>Core Driver Infrastructure</h2></div></div></div><div class="toc"><dl class="toc"><dt><span class="sect2"><a href="drmI915.html#idp1127683628">Runtime Power Management</a></span></dt><dt><span class="sect2"><a href="drmI915.html#idp1127820844">Interrupt Handling</a></span></dt><dt><span class="sect2"><a href="drmI915.html#idp1127853244">Intel GVT-g Guest Support(vGPU)</a></span></dt></dl></div><p> 7 This section covers core driver infrastructure used by both the display 8 and the GEM parts of the driver. 9 </p><div class="sect2"><div class="titlepage"><div><div><h3 class="title"><a name="idp1127683628"></a>Runtime Power Management</h3></div></div></div><div class="toc"><dl class="toc"><dt><span class="refentrytitle"><a href="API---intel-display-power-is-enabled.html"><span class="phrase">__intel_display_power_is_enabled</span></a></span><span class="refpurpose"> — 10 unlocked check for a power domain 11 </span></dt><dt><span class="refentrytitle"><a href="API-intel-display-power-is-enabled.html"><span class="phrase">intel_display_power_is_enabled</span></a></span><span class="refpurpose"> — 12 check for a power domain 13 </span></dt><dt><span class="refentrytitle"><a href="API-intel-display-set-init-power.html"><span class="phrase">intel_display_set_init_power</span></a></span><span class="refpurpose"> — 14 set the initial power domain state 15 </span></dt><dt><span class="refentrytitle"><a href="API-intel-display-power-get.html"><span class="phrase">intel_display_power_get</span></a></span><span class="refpurpose"> — 16 grab a power domain reference 17 </span></dt><dt><span class="refentrytitle"><a href="API-intel-display-power-put.html"><span class="phrase">intel_display_power_put</span></a></span><span class="refpurpose"> — 18 release a power domain reference 19 </span></dt><dt><span class="refentrytitle"><a href="API-intel-power-domains-init.html"><span class="phrase">intel_power_domains_init</span></a></span><span class="refpurpose"> — 20 initializes the power domain structures 21 </span></dt><dt><span class="refentrytitle"><a href="API-intel-power-domains-fini.html"><span class="phrase">intel_power_domains_fini</span></a></span><span class="refpurpose"> — 22 finalizes the power domain structures 23 </span></dt><dt><span class="refentrytitle"><a href="API-intel-power-domains-init-hw.html"><span class="phrase">intel_power_domains_init_hw</span></a></span><span class="refpurpose"> — 24 initialize hardware power domain state 25 </span></dt><dt><span class="refentrytitle"><a href="API-intel-aux-display-runtime-get.html"><span class="phrase">intel_aux_display_runtime_get</span></a></span><span class="refpurpose"> — 26 grab an auxiliary power domain reference 27 </span></dt><dt><span class="refentrytitle"><a href="API-intel-aux-display-runtime-put.html"><span class="phrase">intel_aux_display_runtime_put</span></a></span><span class="refpurpose"> — 28 release an auxiliary power domain reference 29 </span></dt><dt><span class="refentrytitle"><a href="API-intel-runtime-pm-get.html"><span class="phrase">intel_runtime_pm_get</span></a></span><span class="refpurpose"> — 30 grab a runtime pm reference 31 </span></dt><dt><span class="refentrytitle"><a href="API-intel-runtime-pm-get-noresume.html"><span class="phrase">intel_runtime_pm_get_noresume</span></a></span><span class="refpurpose"> — 32 grab a runtime pm reference 33 </span></dt><dt><span class="refentrytitle"><a href="API-intel-runtime-pm-put.html"><span class="phrase">intel_runtime_pm_put</span></a></span><span class="refpurpose"> — 34 release a runtime pm reference 35 </span></dt><dt><span class="refentrytitle"><a href="API-intel-runtime-pm-enable.html"><span class="phrase">intel_runtime_pm_enable</span></a></span><span class="refpurpose"> — 36 enable runtime pm 37 </span></dt><dt><span class="refentrytitle"><a href="API-intel-uncore-forcewake-get.html"><span class="phrase">intel_uncore_forcewake_get</span></a></span><span class="refpurpose"> — 38 grab forcewake domain references 39 </span></dt><dt><span class="refentrytitle"><a href="API-intel-uncore-forcewake-put.html"><span class="phrase">intel_uncore_forcewake_put</span></a></span><span class="refpurpose"> — 40 release a forcewake domain reference 41 </span></dt></dl></div><p> 42 </p><p> 43 The i915 driver supports dynamic enabling and disabling of entire hardware 44 blocks at runtime. This is especially important on the display side where 45 software is supposed to control many power gates manually on recent hardware, 46 since on the GT side a lot of the power management is done by the hardware. 47 But even there some manual control at the device level is required. 48 </p><p> 49 Since i915 supports a diverse set of platforms with a unified codebase and 50 hardware engineers just love to shuffle functionality around between power 51 domains there's a sizeable amount of indirection required. This file provides 52 generic functions to the driver for grabbing and releasing references for 53 abstract power domains. It then maps those to the actual power wells 54 present for a given platform. 55</p></div><div class="sect2"><div class="titlepage"><div><div><h3 class="title"><a name="idp1127820844"></a>Interrupt Handling</h3></div></div></div><div class="toc"><dl class="toc"><dt><span class="refentrytitle"><a href="API-intel-irq-init.html"><span class="phrase">intel_irq_init</span></a></span><span class="refpurpose"> — 56 initializes irq support 57 </span></dt><dt><span class="refentrytitle"><a href="API-intel-hpd-init.html"><span class="phrase">intel_hpd_init</span></a></span><span class="refpurpose"> — 58 initializes and enables hpd support 59 </span></dt><dt><span class="refentrytitle"><a href="re492.html"> 60 .//drivers/gpu/drm/i915/i915_irq.c 61 </a></span><span class="refpurpose"> — 62 Document generation inconsistency 63 </span></dt><dt><span class="refentrytitle"><a href="API-intel-runtime-pm-disable-interrupts.html"><span class="phrase">intel_runtime_pm_disable_interrupts</span></a></span><span class="refpurpose"> — 64 runtime interrupt disabling 65 </span></dt><dt><span class="refentrytitle"><a href="API-intel-runtime-pm-enable-interrupts.html"><span class="phrase">intel_runtime_pm_enable_interrupts</span></a></span><span class="refpurpose"> — 66 runtime interrupt enabling 67 </span></dt></dl></div><p> 68 </p><p> 69 These functions provide the basic support for enabling and disabling the 70 interrupt handling support. There's a lot more functionality in i915_irq.c 71 and related files, but that will be described in separate chapters. 72</p></div><div class="sect2"><div class="titlepage"><div><div><h3 class="title"><a name="idp1127853244"></a>Intel GVT-g Guest Support(vGPU)</h3></div></div></div><div class="toc"><dl class="toc"><dt><span class="refentrytitle"><a href="API-i915-check-vgpu.html"><span class="phrase">i915_check_vgpu</span></a></span><span class="refpurpose"> — 73 detect virtual GPU 74 </span></dt><dt><span class="refentrytitle"><a href="API-intel-vgt-deballoon.html"><span class="phrase">intel_vgt_deballoon</span></a></span><span class="refpurpose"> — 75 deballoon reserved graphics address trunks 76 </span></dt><dt><span class="refentrytitle"><a href="API-intel-vgt-balloon.html"><span class="phrase">intel_vgt_balloon</span></a></span><span class="refpurpose"> — 77 balloon out reserved graphics address trunks 78 </span></dt></dl></div><p> 79 </p><p> 80 Intel GVT-g is a graphics virtualization technology which shares the 81 GPU among multiple virtual machines on a time-sharing basis. Each 82 virtual machine is presented a virtual GPU (vGPU), which has equivalent 83 features as the underlying physical GPU (pGPU), so i915 driver can run 84 seamlessly in a virtual machine. This file provides vGPU specific 85 optimizations when running in a virtual machine, to reduce the complexity 86 of vGPU emulation and to improve the overall performance. 87 </p><p> 88 A primary function introduced here is so-called <span class="quote">“<span class="quote">address space ballooning</span>”</span> 89 technique. Intel GVT-g partitions global graphics memory among multiple VMs, 90 so each VM can directly access a portion of the memory without hypervisor's 91 intervention, e.g. filling textures or queuing commands. However with the 92 partitioning an unmodified i915 driver would assume a smaller graphics 93 memory starting from address ZERO, then requires vGPU emulation module to 94 translate the graphics address between 'guest view' and 'host view', for 95 all registers and command opcodes which contain a graphics memory address. 96 To reduce the complexity, Intel GVT-g introduces <span class="quote">“<span class="quote">address space ballooning</span>”</span>, 97 by telling the exact partitioning knowledge to each guest i915 driver, which 98 then reserves and prevents non-allocated portions from allocation. Thus vGPU 99 emulation module only needs to scan and validate graphics addresses without 100 complexity of address translation. 101 </p><p> 102</p></div></div></div><div class="navfooter"><hr><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="drmDrivers.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="drmDrivers.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="API---intel-display-power-is-enabled.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Part II. DRM Drivers </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> <span class="phrase">__intel_display_power_is_enabled</span></td></tr></table></div></body></html> 103