1<html><head><meta http-equiv="Content-Type" content="text/html; charset=ANSI_X3.4-1968"><title>Display Hardware Handling</title><meta name="generator" content="DocBook XSL Stylesheets V1.78.1"><link rel="home" href="index.html" title="Linux DRM Developer's Guide"><link rel="up" href="drmI915.html" title="Chapter 4. drm/i915 Intel GFX Driver"><link rel="prev" href="API-intel-vgt-balloon.html" title="intel_vgt_balloon"><link rel="next" href="API-intel-mark-fb-busy.html" title="intel_mark_fb_busy"></head><body bgcolor="white" text="black" link="#0000FF" vlink="#840084" alink="#0000FF"><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Display Hardware Handling</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="API-intel-vgt-balloon.html">Prev</a> </td><th width="60%" align="center">Chapter 4. drm/i915 Intel GFX Driver</th><td width="20%" align="right"> <a accesskey="n" href="API-intel-mark-fb-busy.html">Next</a></td></tr></table><hr></div><div class="sect1"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="idp1127881460"></a>Display Hardware Handling</h2></div></div></div><div class="toc"><dl class="toc"><dt><span class="sect2"><a href="ch04s02.html#idp1127882228">Mode Setting Infrastructure</a></span></dt><dt><span class="sect2"><a href="ch04s02.html#idp1127883116">Frontbuffer Tracking</a></span></dt><dt><span class="sect2"><a href="ch04s02.html#idp1127966068">Display FIFO Underrun Reporting</a></span></dt><dt><span class="sect2"><a href="ch04s02.html#idp1128014948">Plane Configuration</a></span></dt><dt><span class="sect2"><a href="ch04s02.html#idp1128015892">Atomic Plane Helpers</a></span></dt><dt><span class="sect2"><a href="ch04s02.html#idp1128065636">Output Probing</a></span></dt><dt><span class="sect2"><a href="ch04s02.html#idp1128066516">High Definition Audio</a></span></dt><dt><span class="sect2"><a href="ch04s02.html#idp1128104188">Panel Self Refresh PSR (PSR/SRD)</a></span></dt><dt><span class="sect2"><a href="ch04s02.html#idp1128147260">Frame Buffer Compression (FBC)</a></span></dt><dt><span class="sect2"><a href="ch04s02.html#idp1128179172">Display Refresh Rate Switching (DRRS)</a></span></dt><dt><span class="sect2"><a href="ch04s02.html#idp1128232364">DPIO</a></span></dt></dl></div><p> 2 This section covers everything related to the display hardware including 3 the mode setting infrastructure, plane, sprite and cursor handling and 4 display, output probing and related topics. 5 </p><div class="sect2"><div class="titlepage"><div><div><h3 class="title"><a name="idp1127882228"></a>Mode Setting Infrastructure</h3></div></div></div><p> 6 The i915 driver is thus far the only DRM driver which doesn't use the 7 common DRM helper code to implement mode setting sequences. Thus it 8 has its own tailor-made infrastructure for executing a display 9 configuration change. 10 </p></div><div class="sect2"><div class="titlepage"><div><div><h3 class="title"><a name="idp1127883116"></a>Frontbuffer Tracking</h3></div></div></div><div class="toc"><dl class="toc"><dt><span class="refentrytitle"><a href="API-intel-mark-fb-busy.html"><span class="phrase">intel_mark_fb_busy</span></a></span><span class="refpurpose"> — 11 mark given planes as busy 12 </span></dt><dt><span class="refentrytitle"><a href="API-intel-fb-obj-invalidate.html"><span class="phrase">intel_fb_obj_invalidate</span></a></span><span class="refpurpose"> — 13 invalidate frontbuffer object 14 </span></dt><dt><span class="refentrytitle"><a href="API-intel-frontbuffer-flush.html"><span class="phrase">intel_frontbuffer_flush</span></a></span><span class="refpurpose"> — 15 flush frontbuffer 16 </span></dt><dt><span class="refentrytitle"><a href="API-intel-fb-obj-flush.html"><span class="phrase">intel_fb_obj_flush</span></a></span><span class="refpurpose"> — 17 flush frontbuffer object 18 </span></dt><dt><span class="refentrytitle"><a href="API-intel-frontbuffer-flip-prepare.html"><span class="phrase">intel_frontbuffer_flip_prepare</span></a></span><span class="refpurpose"> — 19 prepare asynchronous frontbuffer flip 20 </span></dt><dt><span class="refentrytitle"><a href="API-intel-frontbuffer-flip-complete.html"><span class="phrase">intel_frontbuffer_flip_complete</span></a></span><span class="refpurpose"> — 21 complete asynchronous frontbuffer flip 22 </span></dt><dt><span class="refentrytitle"><a href="API-intel-frontbuffer-flip.html"><span class="phrase">intel_frontbuffer_flip</span></a></span><span class="refpurpose"> — 23 synchronous frontbuffer flip 24 </span></dt><dt><span class="refentrytitle"><a href="API-i915-gem-track-fb.html"><span class="phrase">i915_gem_track_fb</span></a></span><span class="refpurpose"> — 25 update frontbuffer tracking 26 </span></dt></dl></div><p> 27 </p><p> 28 Many features require us to track changes to the currently active 29 frontbuffer, especially rendering targeted at the frontbuffer. 30 </p><p> 31 To be able to do so GEM tracks frontbuffers using a bitmask for all possible 32 frontbuffer slots through <code class="function">i915_gem_track_fb</code>. The function in this file are 33 then called when the contents of the frontbuffer are invalidated, when 34 frontbuffer rendering has stopped again to flush out all the changes and when 35 the frontbuffer is exchanged with a flip. Subsystems interested in 36 frontbuffer changes (e.g. PSR, FBC, DRRS) should directly put their callbacks 37 into the relevant places and filter for the frontbuffer slots that they are 38 interested int. 39 </p><p> 40 On a high level there are two types of powersaving features. The first one 41 work like a special cache (FBC and PSR) and are interested when they should 42 stop caching and when to restart caching. This is done by placing callbacks 43 into the invalidate and the flush functions: At invalidate the caching must 44 be stopped and at flush time it can be restarted. And maybe they need to know 45 when the frontbuffer changes (e.g. when the hw doesn't initiate an invalidate 46 and flush on its own) which can be achieved with placing callbacks into the 47 flip functions. 48 </p><p> 49 The other type of display power saving feature only cares about busyness 50 (e.g. DRRS). In that case all three (invalidate, flush and flip) indicate 51 busyness. There is no direct way to detect idleness. Instead an idle timer 52 work delayed work should be started from the flush and flip functions and 53 cancelled as soon as busyness is detected. 54 </p><p> 55 Note that there's also an older frontbuffer activity tracking scheme which 56 just tracks general activity. This is done by the various mark_busy and 57 mark_idle functions. For display power management features using these 58 functions is deprecated and should be avoided. 59</p></div><div class="sect2"><div class="titlepage"><div><div><h3 class="title"><a name="idp1127966068"></a>Display FIFO Underrun Reporting</h3></div></div></div><div class="toc"><dl class="toc"><dt><span class="refentrytitle"><a href="API-i9xx-check-fifo-underruns.html"><span class="phrase">i9xx_check_fifo_underruns</span></a></span><span class="refpurpose"> — 60 check for fifo underruns 61 </span></dt><dt><span class="refentrytitle"><a href="API-intel-set-cpu-fifo-underrun-reporting.html"><span class="phrase">intel_set_cpu_fifo_underrun_reporting</span></a></span><span class="refpurpose"> — 62 set cpu fifo underrrun reporting state 63 </span></dt><dt><span class="refentrytitle"><a href="API-intel-set-pch-fifo-underrun-reporting.html"><span class="phrase">intel_set_pch_fifo_underrun_reporting</span></a></span><span class="refpurpose"> — 64 set PCH fifo underrun reporting state 65 </span></dt><dt><span class="refentrytitle"><a href="API-intel-cpu-fifo-underrun-irq-handler.html"><span class="phrase">intel_cpu_fifo_underrun_irq_handler</span></a></span><span class="refpurpose"> — 66 handle CPU fifo underrun interrupt 67 </span></dt><dt><span class="refentrytitle"><a href="API-intel-pch-fifo-underrun-irq-handler.html"><span class="phrase">intel_pch_fifo_underrun_irq_handler</span></a></span><span class="refpurpose"> — 68 handle PCH fifo underrun interrupt 69 </span></dt></dl></div><p> 70 </p><p> 71 The i915 driver checks for display fifo underruns using the interrupt signals 72 provided by the hardware. This is enabled by default and fairly useful to 73 debug display issues, especially watermark settings. 74 </p><p> 75 If an underrun is detected this is logged into dmesg. To avoid flooding logs 76 and occupying the cpu underrun interrupts are disabled after the first 77 occurrence until the next modeset on a given pipe. 78 </p><p> 79 Note that underrun detection on gmch platforms is a bit more ugly since there 80 is no interrupt (despite that the signalling bit is in the PIPESTAT pipe 81 interrupt register). Also on some other platforms underrun interrupts are 82 shared, which means that if we detect an underrun we need to disable underrun 83 reporting on all pipes. 84 </p><p> 85 The code also supports underrun detection on the PCH transcoder. 86</p></div><div class="sect2"><div class="titlepage"><div><div><h3 class="title"><a name="idp1128014948"></a>Plane Configuration</h3></div></div></div><p> 87 This section covers plane configuration and composition with the 88 primary plane, sprites, cursors and overlays. This includes the 89 infrastructure to do atomic vsync'ed updates of all this state and 90 also tightly coupled topics like watermark setup and computation, 91 framebuffer compression and panel self refresh. 92 </p></div><div class="sect2"><div class="titlepage"><div><div><h3 class="title"><a name="idp1128015892"></a>Atomic Plane Helpers</h3></div></div></div><div class="toc"><dl class="toc"><dt><span class="refentrytitle"><a href="API-intel-create-plane-state.html"><span class="phrase">intel_create_plane_state</span></a></span><span class="refpurpose"> — 93 create plane state object 94 </span></dt><dt><span class="refentrytitle"><a href="API-intel-plane-duplicate-state.html"><span class="phrase">intel_plane_duplicate_state</span></a></span><span class="refpurpose"> — 95 duplicate plane state 96 </span></dt><dt><span class="refentrytitle"><a href="API-intel-plane-destroy-state.html"><span class="phrase">intel_plane_destroy_state</span></a></span><span class="refpurpose"> — 97 destroy plane state 98 </span></dt><dt><span class="refentrytitle"><a href="API-intel-plane-atomic-get-property.html"><span class="phrase">intel_plane_atomic_get_property</span></a></span><span class="refpurpose"> — 99 fetch plane property value 100 </span></dt><dt><span class="refentrytitle"><a href="API-intel-plane-atomic-set-property.html"><span class="phrase">intel_plane_atomic_set_property</span></a></span><span class="refpurpose"> — 101 set plane property value 102 </span></dt></dl></div><p> 103 </p><p> 104 The functions here are used by the atomic plane helper functions to 105 implement legacy plane updates (i.e., drm_plane-><code class="function">update_plane</code> and 106 drm_plane-><code class="function">disable_plane</code>). This allows plane updates to use the 107 atomic state infrastructure and perform plane updates as separate 108 prepare/check/commit/cleanup steps. 109</p></div><div class="sect2"><div class="titlepage"><div><div><h3 class="title"><a name="idp1128065636"></a>Output Probing</h3></div></div></div><p> 110 This section covers output probing and related infrastructure like the 111 hotplug interrupt storm detection and mitigation code. Note that the 112 i915 driver still uses most of the common DRM helper code for output 113 probing, so those sections fully apply. 114 </p></div><div class="sect2"><div class="titlepage"><div><div><h3 class="title"><a name="idp1128066516"></a>High Definition Audio</h3></div></div></div><div class="toc"><dl class="toc"><dt><span class="refentrytitle"><a href="API-intel-audio-codec-enable.html"><span class="phrase">intel_audio_codec_enable</span></a></span><span class="refpurpose"> — 115 Enable the audio codec for HD audio 116 </span></dt><dt><span class="refentrytitle"><a href="API-intel-audio-codec-disable.html"><span class="phrase">intel_audio_codec_disable</span></a></span><span class="refpurpose"> — 117 Disable the audio codec for HD audio 118 </span></dt><dt><span class="refentrytitle"><a href="API-intel-init-audio.html"><span class="phrase">intel_init_audio</span></a></span><span class="refpurpose"> — 119 Set up chip specific audio functions 120 </span></dt><dt><span class="refentrytitle"><a href="API-i915-audio-component-init.html"><span class="phrase">i915_audio_component_init</span></a></span><span class="refpurpose"> — 121 initialize and register the audio component 122 </span></dt><dt><span class="refentrytitle"><a href="API-i915-audio-component-cleanup.html"><span class="phrase">i915_audio_component_cleanup</span></a></span><span class="refpurpose"> — 123 deregister the audio component 124 </span></dt></dl></div><p> 125 </p><p> 126 The graphics and audio drivers together support High Definition Audio over 127 HDMI and Display Port. The audio programming sequences are divided into audio 128 codec and controller enable and disable sequences. The graphics driver 129 handles the audio codec sequences, while the audio driver handles the audio 130 controller sequences. 131 </p><p> 132 The disable sequences must be performed before disabling the transcoder or 133 port. The enable sequences may only be performed after enabling the 134 transcoder and port, and after completed link training. 135 </p><p> 136 The codec and controller sequences could be done either parallel or serial, 137 but generally the ELDV/PD change in the codec sequence indicates to the audio 138 driver that the controller sequence should start. Indeed, most of the 139 co-operation between the graphics and audio drivers is handled via audio 140 related registers. (The notable exception is the power management, not 141 covered here.) 142</p></div><div class="sect2"><div class="titlepage"><div><div><h3 class="title"><a name="idp1128104188"></a>Panel Self Refresh PSR (PSR/SRD)</h3></div></div></div><div class="toc"><dl class="toc"><dt><span class="refentrytitle"><a href="API-intel-psr-enable.html"><span class="phrase">intel_psr_enable</span></a></span><span class="refpurpose"> — 143 Enable PSR 144 </span></dt><dt><span class="refentrytitle"><a href="API-intel-psr-disable.html"><span class="phrase">intel_psr_disable</span></a></span><span class="refpurpose"> — 145 Disable PSR 146 </span></dt><dt><span class="refentrytitle"><a href="API-intel-psr-invalidate.html"><span class="phrase">intel_psr_invalidate</span></a></span><span class="refpurpose"> — 147 Invalidade PSR 148 </span></dt><dt><span class="refentrytitle"><a href="API-intel-psr-flush.html"><span class="phrase">intel_psr_flush</span></a></span><span class="refpurpose"> — 149 Flush PSR 150 </span></dt><dt><span class="refentrytitle"><a href="API-intel-psr-init.html"><span class="phrase">intel_psr_init</span></a></span><span class="refpurpose"> — 151 Init basic PSR work and mutex. 152 </span></dt></dl></div><p> 153 </p><p> 154 Since Haswell Display controller supports Panel Self-Refresh on display 155 panels witch have a remote frame buffer (RFB) implemented according to PSR 156 spec in eDP1.3. PSR feature allows the display to go to lower standby states 157 when system is idle but display is on as it eliminates display refresh 158 request to DDR memory completely as long as the frame buffer for that 159 display is unchanged. 160 </p><p> 161 Panel Self Refresh must be supported by both Hardware (source) and 162 Panel (sink). 163 </p><p> 164 PSR saves power by caching the framebuffer in the panel RFB, which allows us 165 to power down the link and memory controller. For DSI panels the same idea 166 is called <span class="quote">“<span class="quote">manual mode</span>”</span>. 167 </p><p> 168 The implementation uses the hardware-based PSR support which automatically 169 enters/exits self-refresh mode. The hardware takes care of sending the 170 required DP aux message and could even retrain the link (that part isn't 171 enabled yet though). The hardware also keeps track of any frontbuffer 172 changes to know when to exit self-refresh mode again. Unfortunately that 173 part doesn't work too well, hence why the i915 PSR support uses the 174 software frontbuffer tracking to make sure it doesn't miss a screen 175 update. For this integration <code class="function">intel_psr_invalidate</code> and <code class="function">intel_psr_flush</code> 176 get called by the frontbuffer tracking code. Note that because of locking 177 issues the self-refresh re-enable code is done from a work queue, which 178 must be correctly synchronized/cancelled when shutting down the pipe." 179</p></div><div class="sect2"><div class="titlepage"><div><div><h3 class="title"><a name="idp1128147260"></a>Frame Buffer Compression (FBC)</h3></div></div></div><div class="toc"><dl class="toc"><dt><span class="refentrytitle"><a href="API-intel-fbc-enabled.html"><span class="phrase">intel_fbc_enabled</span></a></span><span class="refpurpose"> — 180 Is FBC enabled? 181 </span></dt><dt><span class="refentrytitle"><a href="API-intel-fbc-disable.html"><span class="phrase">intel_fbc_disable</span></a></span><span class="refpurpose"> — 182 disable FBC 183 </span></dt><dt><span class="refentrytitle"><a href="API-intel-fbc-update.html"><span class="phrase">intel_fbc_update</span></a></span><span class="refpurpose"> — 184 enable/disable FBC as needed 185 </span></dt><dt><span class="refentrytitle"><a href="API-intel-fbc-init.html"><span class="phrase">intel_fbc_init</span></a></span><span class="refpurpose"> — 186 Initialize FBC 187 </span></dt></dl></div><p> 188 </p><p> 189 FBC tries to save memory bandwidth (and so power consumption) by 190 compressing the amount of memory used by the display. It is total 191 transparent to user space and completely handled in the kernel. 192 </p><p> 193 The benefits of FBC are mostly visible with solid backgrounds and 194 variation-less patterns. It comes from keeping the memory footprint small 195 and having fewer memory pages opened and accessed for refreshing the display. 196 </p><p> 197 i915 is responsible to reserve stolen memory for FBC and configure its 198 offset on proper registers. The hardware takes care of all 199 compress/decompress. However there are many known cases where we have to 200 forcibly disable it to allow proper screen updates. 201</p></div><div class="sect2"><div class="titlepage"><div><div><h3 class="title"><a name="idp1128179172"></a>Display Refresh Rate Switching (DRRS)</h3></div></div></div><div class="toc"><dl class="toc"><dt><span class="refentrytitle"><a href="API-intel-dp-set-drrs-state.html"><span class="phrase">intel_dp_set_drrs_state</span></a></span><span class="refpurpose"> — 202 program registers for RR switch to take effect 203 </span></dt><dt><span class="refentrytitle"><a href="API-intel-edp-drrs-enable.html"><span class="phrase">intel_edp_drrs_enable</span></a></span><span class="refpurpose"> — 204 init drrs struct if supported 205 </span></dt><dt><span class="refentrytitle"><a href="API-intel-edp-drrs-disable.html"><span class="phrase">intel_edp_drrs_disable</span></a></span><span class="refpurpose"> — 206 Disable DRRS 207 </span></dt><dt><span class="refentrytitle"><a href="API-intel-edp-drrs-invalidate.html"><span class="phrase">intel_edp_drrs_invalidate</span></a></span><span class="refpurpose"> — 208 Invalidate DRRS 209 </span></dt><dt><span class="refentrytitle"><a href="API-intel-edp-drrs-flush.html"><span class="phrase">intel_edp_drrs_flush</span></a></span><span class="refpurpose"> — 210 Flush DRRS 211 </span></dt><dt><span class="refentrytitle"><a href="API-intel-dp-drrs-init.html"><span class="phrase">intel_dp_drrs_init</span></a></span><span class="refpurpose"> — 212 Init basic DRRS work and mutex. 213 </span></dt></dl></div><p> 214 </p><p> 215 Display Refresh Rate Switching (DRRS) is a power conservation feature 216 which enables swtching between low and high refresh rates, 217 dynamically, based on the usage scenario. This feature is applicable 218 for internal panels. 219 </p><p> 220 Indication that the panel supports DRRS is given by the panel EDID, which 221 would list multiple refresh rates for one resolution. 222 </p><p> 223 DRRS is of 2 types - static and seamless. 224 Static DRRS involves changing refresh rate (RR) by doing a full modeset 225 (may appear as a blink on screen) and is used in dock-undock scenario. 226 Seamless DRRS involves changing RR without any visual effect to the user 227 and can be used during normal system usage. This is done by programming 228 certain registers. 229 </p><p> 230 Support for static/seamless DRRS may be indicated in the VBT based on 231 inputs from the panel spec. 232 </p><p> 233 DRRS saves power by switching to low RR based on usage scenarios. 234 </p><p> 235 eDP DRRS:- 236 The implementation is based on frontbuffer tracking implementation. 237 When there is a disturbance on the screen triggered by user activity or a 238 periodic system activity, DRRS is disabled (RR is changed to high RR). 239 When there is no movement on screen, after a timeout of 1 second, a switch 240 to low RR is made. 241 For integration with frontbuffer tracking code, 242 <code class="function">intel_edp_drrs_invalidate</code> and <code class="function">intel_edp_drrs_flush</code> are called. 243 </p><p> 244 DRRS can be further extended to support other internal panels and also 245 the scenario of video playback wherein RR is set based on the rate 246 requested by userspace. 247</p></div><div class="sect2"><div class="titlepage"><div><div><h3 class="title"><a name="idp1128232364"></a>DPIO</h3></div></div></div><p> 248 </p><p> 249 VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI 250 ports. DPIO is the name given to such a display PHY. These PHYs 251 don't follow the standard programming model using direct MMIO 252 registers, and instead their registers must be accessed trough IOSF 253 sideband. VLV has one such PHY for driving ports B and C, and CHV 254 adds another PHY for driving port D. Each PHY responds to specific 255 IOSF-SB port. 256 </p><p> 257 Each display PHY is made up of one or two channels. Each channel 258 houses a common lane part which contains the PLL and other common 259 logic. CH0 common lane also contains the IOSF-SB logic for the 260 Common Register Interface (CRI) ie. the DPIO registers. CRI clock 261 must be running when any DPIO registers are accessed. 262 </p><p> 263 In addition to having their own registers, the PHYs are also 264 controlled through some dedicated signals from the display 265 controller. These include PLL reference clock enable, PLL enable, 266 and CRI clock selection, for example. 267 </p><p> 268 Eeach channel also has two splines (also called data lanes), and 269 each spline is made up of one Physical Access Coding Sub-Layer 270 (PCS) block and two TX lanes. So each channel has two PCS blocks 271 and four TX lanes. The TX lanes are used as DP lanes or TMDS 272 data/clock pairs depending on the output type. 273 </p><p> 274 Additionally the PHY also contains an AUX lane with AUX blocks 275 for each channel. This is used for DP AUX communication, but 276 this fact isn't really relevant for the driver since AUX is 277 controlled from the display controller side. No DPIO registers 278 need to be accessed during AUX communication, 279 </p><p> 280 Generally the common lane corresponds to the pipe and 281 the spline (PCS/TX) corresponds to the port. 282 </p><p> 283 For dual channel PHY (VLV/CHV): 284 </p><p> 285 pipe A == CMN/PLL/REF CH0 286 </p><p> 287 pipe B == CMN/PLL/REF CH1 288 </p><p> 289 port B == PCS/TX CH0 290 </p><p> 291 port C == PCS/TX CH1 292 </p><p> 293 This is especially important when we cross the streams 294 ie. drive port B with pipe B, or port C with pipe A. 295 </p><p> 296 For single channel PHY (CHV): 297 </p><p> 298 pipe C == CMN/PLL/REF CH0 299 </p><p> 300 port D == PCS/TX CH0 301 </p><p> 302 Note: digital port B is DDI0, digital port C is DDI1, 303 digital port D is DDI2 304</p><div class="table"><a name="dpiox2"></a><p class="title"><b>Table 4.1. Dual channel PHY (VLV/CHV)</b></p><div class="table-contents"><table summary="Dual channel PHY (VLV/CHV)" border="1"><colgroup><col class="c0"><col class="c1"><col class="c2"><col class="c3"><col class="c4"><col class="c5"><col class="c6"><col class="c7"></colgroup><thead><tr><th colspan="4">CH0</th><th colspan="4">CH1</th></tr></thead><tbody align="center" valign="top"><tr><td colspan="4" align="center" valign="top">CMN/PLL/REF</td><td colspan="4" align="center" valign="top">CMN/PLL/REF</td></tr><tr><td colspan="2" align="center" valign="top">PCS01</td><td colspan="2" align="center" valign="top">PCS23</td><td colspan="2" align="center" valign="top">PCS01</td><td colspan="2" align="center" valign="top">PCS23</td></tr><tr><td align="center" valign="top">TX0</td><td align="center" valign="top">TX1</td><td align="center" valign="top">TX2</td><td align="center" valign="top">TX3</td><td align="center" valign="top">TX0</td><td align="center" valign="top">TX1</td><td align="center" valign="top">TX2</td><td align="center" valign="top">TX3</td></tr><tr><td colspan="4" align="center" valign="top">DDI0</td><td colspan="4" align="center" valign="top">DDI1</td></tr></tbody></table></div></div><br class="table-break"><div class="table"><a name="dpiox1"></a><p class="title"><b>Table 4.2. Single channel PHY (CHV)</b></p><div class="table-contents"><table summary="Single channel PHY (CHV)" border="1"><colgroup><col class="c0"><col class="c1"><col class="c2"><col class="c3"></colgroup><thead><tr><th colspan="4">CH0</th></tr></thead><tbody align="center" valign="top"><tr><td colspan="4" align="center" valign="top">CMN/PLL/REF</td></tr><tr><td colspan="2" align="center" valign="top">PCS01</td><td colspan="2" align="center" valign="top">PCS23</td></tr><tr><td align="center" valign="top">TX0</td><td align="center" valign="top">TX1</td><td align="center" valign="top">TX2</td><td align="center" valign="top">TX3</td></tr><tr><td colspan="4" align="center" valign="top">DDI2</td></tr></tbody></table></div></div><br class="table-break"></div></div><div class="navfooter"><hr><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="API-intel-vgt-balloon.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="drmI915.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="API-intel-mark-fb-busy.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top"><span class="phrase">intel_vgt_balloon</span> </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> <span class="phrase">intel_mark_fb_busy</span></td></tr></table></div></body></html> 305