1<html><head><meta http-equiv="Content-Type" content="text/html; charset=ANSI_X3.4-1968"><title>Accessing the device</title><meta name="generator" content="DocBook XSL Stylesheets V1.78.1"><link rel="home" href="index.html" title="Bus-Independent Device Accesses"><link rel="up" href="mmio.html" title="Chapter 3. Memory Mapped IO"><link rel="prev" href="mmio.html" title="Chapter 3. Memory Mapped IO"><link rel="next" href="port_space_accesses.html" title="Chapter 4. Port Space Accesses"></head><body bgcolor="white" text="black" link="#0000FF" vlink="#840084" alink="#0000FF"><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Accessing the device</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="mmio.html">Prev</a> </td><th width="60%" align="center">Chapter 3. Memory Mapped IO</th><td width="20%" align="right"> <a accesskey="n" href="port_space_accesses.html">Next</a></td></tr></table><hr></div><div class="sect1"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="accessing_the_device"></a>Accessing the device</h2></div></div></div><p> 2 The part of the interface most used by drivers is reading and 3 writing memory-mapped registers on the device. Linux provides 4 interfaces to read and write 8-bit, 16-bit, 32-bit and 64-bit 5 quantities. Due to a historical accident, these are named byte, 6 word, long and quad accesses. Both read and write accesses are 7 supported; there is no prefetch support at this time. 8 </p><p> 9 The functions are named <code class="function">readb</code>, 10 <code class="function">readw</code>, <code class="function">readl</code>, 11 <code class="function">readq</code>, <code class="function">readb_relaxed</code>, 12 <code class="function">readw_relaxed</code>, <code class="function">readl_relaxed</code>, 13 <code class="function">readq_relaxed</code>, <code class="function">writeb</code>, 14 <code class="function">writew</code>, <code class="function">writel</code> and 15 <code class="function">writeq</code>. 16 </p><p> 17 Some devices (such as framebuffers) would like to use larger 18 transfers than 8 bytes at a time. For these devices, the 19 <code class="function">memcpy_toio</code>, <code class="function">memcpy_fromio</code> 20 and <code class="function">memset_io</code> functions are provided. 21 Do not use memset or memcpy on IO addresses; they 22 are not guaranteed to copy data in order. 23 </p><p> 24 The read and write functions are defined to be ordered. That is the 25 compiler is not permitted to reorder the I/O sequence. When the 26 ordering can be compiler optimised, you can use <code class="function"> 27 __readb</code> and friends to indicate the relaxed ordering. Use 28 this with care. 29 </p><p> 30 While the basic functions are defined to be synchronous with respect 31 to each other and ordered with respect to each other the busses the 32 devices sit on may themselves have asynchronicity. In particular many 33 authors are burned by the fact that PCI bus writes are posted 34 asynchronously. A driver author must issue a read from the same 35 device to ensure that writes have occurred in the specific cases the 36 author cares. This kind of property cannot be hidden from driver 37 writers in the API. In some cases, the read used to flush the device 38 may be expected to fail (if the card is resetting, for example). In 39 that case, the read should be done from config space, which is 40 guaranteed to soft-fail if the card doesn't respond. 41 </p><p> 42 The following is an example of flushing a write to a device when 43 the driver would like to ensure the write's effects are visible prior 44 to continuing execution. 45 </p><pre class="programlisting"> 46static inline void 47qla1280_disable_intrs(struct scsi_qla_host *ha) 48{ 49 struct device_reg *reg; 50 51 reg = ha->iobase; 52 /* disable risc and host interrupts */ 53 WRT_REG_WORD(&reg->ictrl, 0); 54 /* 55 * The following read will ensure that the above write 56 * has been received by the device before we return from this 57 * function. 58 */ 59 RD_REG_WORD(&reg->ictrl); 60 ha->flags.ints_enabled = 0; 61} 62</pre><p> 63 In addition to write posting, on some large multiprocessing systems 64 (e.g. SGI Challenge, Origin and Altix machines) posted writes won't 65 be strongly ordered coming from different CPUs. Thus it's important 66 to properly protect parts of your driver that do memory-mapped writes 67 with locks and use the <code class="function">mmiowb</code> to make sure they 68 arrive in the order intended. Issuing a regular <code class="function">readX 69 </code> will also ensure write ordering, but should only be used 70 when the driver has to be sure that the write has actually arrived 71 at the device (not that it's simply ordered with respect to other 72 writes), since a full <code class="function">readX</code> is a relatively 73 expensive operation. 74 </p><p> 75 Generally, one should use <code class="function">mmiowb</code> prior to 76 releasing a spinlock that protects regions using <code class="function">writeb 77 </code> or similar functions that aren't surrounded by <code class="function"> 78 readb</code> calls, which will ensure ordering and flushing. The 79 following pseudocode illustrates what might occur if write ordering 80 isn't guaranteed via <code class="function">mmiowb</code> or one of the 81 <code class="function">readX</code> functions. 82 </p><pre class="programlisting"> 83CPU A: spin_lock_irqsave(&dev_lock, flags) 84CPU A: ... 85CPU A: writel(newval, ring_ptr); 86CPU A: spin_unlock_irqrestore(&dev_lock, flags) 87 ... 88CPU B: spin_lock_irqsave(&dev_lock, flags) 89CPU B: writel(newval2, ring_ptr); 90CPU B: ... 91CPU B: spin_unlock_irqrestore(&dev_lock, flags) 92</pre><p> 93 In the case above, newval2 could be written to ring_ptr before 94 newval. Fixing it is easy though: 95 </p><pre class="programlisting"> 96CPU A: spin_lock_irqsave(&dev_lock, flags) 97CPU A: ... 98CPU A: writel(newval, ring_ptr); 99CPU A: mmiowb(); /* ensure no other writes beat us to the device */ 100CPU A: spin_unlock_irqrestore(&dev_lock, flags) 101 ... 102CPU B: spin_lock_irqsave(&dev_lock, flags) 103CPU B: writel(newval2, ring_ptr); 104CPU B: ... 105CPU B: mmiowb(); 106CPU B: spin_unlock_irqrestore(&dev_lock, flags) 107</pre><p> 108 See tg3.c for a real world example of how to use <code class="function">mmiowb 109 </code> 110 </p><p> 111 PCI ordering rules also guarantee that PIO read responses arrive 112 after any outstanding DMA writes from that bus, since for some devices 113 the result of a <code class="function">readb</code> call may signal to the 114 driver that a DMA transaction is complete. In many cases, however, 115 the driver may want to indicate that the next 116 <code class="function">readb</code> call has no relation to any previous DMA 117 writes performed by the device. The driver can use 118 <code class="function">readb_relaxed</code> for these cases, although only 119 some platforms will honor the relaxed semantics. Using the relaxed 120 read functions will provide significant performance benefits on 121 platforms that support it. The qla2xxx driver provides examples 122 of how to use <code class="function">readX_relaxed</code>. In many cases, 123 a majority of the driver's <code class="function">readX</code> calls can 124 safely be converted to <code class="function">readX_relaxed</code> calls, since 125 only a few will indicate or depend on DMA completion. 126 </p></div><div class="navfooter"><hr><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="mmio.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="mmio.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="port_space_accesses.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">Chapter 3. Memory Mapped IO </td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top"> Chapter 4. Port Space Accesses</td></tr></table></div></body></html> 127